DDR/LPDDR Verification Engineer – Hybrid, Barcelona

Hireroo Ltd.¿Es este su próximo empleo? Descúbralo leyendo la descripción completa a continuación y no dude en enviar su candidatura.in Barcelona, Spain is seeking a Digital Verification Engineer to perform functional verification of DDR/LPDDR memory interfaces within complex ASIC/So C designs.You will develop and maintain System Verilog/UVM...

Hireroo Ltd is seeking a Lead Design Verification Engineer in Barcelona, Spain, with hybrid work style (4 days in office, 1 day from home). You will own verification strategy and UVM environments for DDR/LPDDR memory interfaces across ASIC/SoC designs.Lead a team, mentor engineers, and collaborate with RTL, architecture and firmware teams to ensure...

Specialization: Semiconductor Design and Functional Verification Job Description Our partner is looking for a Digital Verification Engineer to perform functional verification of DDR/LPDDR memory interfaces within complex ASIC and SoC designs. You will develop and maintain SystemVerilog/UVM testbenches, debug protocol issues and drive coverage closure,...

Specialization: Semiconductor Design and Functional Verification Job Description Our partner is looking for a Lead Design Verification Engineer to lead functional verification of DDR/LPDDR memory interfaces within complex ASIC and SoC designs. You will take ownership of verification strategy, UVM environments and coverage closure, ensuring functional...

Hireroo Ltd is seeking a Lead Design Verification Engineer in Barcelona, Spain, with hybrid work style (4 days in office, 1 day from home). You will own verification strategy and UVM environments for DDR/LPDDR memory interfaces across ASIC/SoC designs.Lead a team, mentor engineers, and collaborate with RTL, architecture and firmware teams to ensure...

We are seeking a Lead Digital Verification Engineer to lead subsystem and IP‑level functional verification of high‑speed interface protocol blocks in our AI chips - namely DDR/LPDDR Memory Interfaces. You will guide a team of highly skilled verification engineers to deliver sign‑off‑quality designs, collaborating closely with RTL design, SoC...

We are seeking a Digital Verification Engineer to perform subsystem and IP‑level functional verification of high‑speed interface protocol blocks in our AI chips - namely DDR/LPDDR Memory Interfaces.You will join a team of highly skilled verification engineers to deliver sign‑off‑quality designs, collaborating closely with RTL design, SoC...

Hireroo Ltd is seeking a Lead Design Verification Engineer in Barcelona, Spain, with hybrid work style (4 days in office, 1 day from home). You will own verification strategy and UVM environments for DDR/LPDDR memory interfaces across ASIC/SoC designs.Lead a team, mentor engineers, and collaborate with RTL, architecture and firmware teams to ensure...

Specialization: Semiconductor Design and Functional Verification Job Description Our partner is looking for a Lead Design Verification Engineer to lead functional verification of DDR/LPDDR memory interfaces within complex ASIC and SoC designs. You will take ownership of verification strategy, UVM environments and coverage closure, ensuring functional...