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Principal Digital Verification Engineer
hace 2 meses
We are seeking a seasoned Principal Digital Verification Engineer to join our team at Epsilonr. This pivotal role involves designing and verifying products that may encompass power management, signal management, and mixed-signal functionalities.
Key Responsibilities- Define and Develop Digital Verification Environments: Create and implement UVM and SystemVerilog-based Digital Verification environments for complex digital and mixed-signal ICs.
- Standardize and Develop Verification IPs (VIPs): Standardize, define, develop, and document Verification IPs (VIPs) for use in Digital Verification environments.
- Integrate VIPs into Digital Verification Environments: Integrate VIPs into the project's Digital Verification environment to ensure seamless verification.
- Define Digital Verification Metrics: Define Digital Verification Metrics for RTL and Gate-Level Verification to ensure comprehensive verification coverage.
- Develop and Implement Test Plans: Develop and implement Test Plans for comprehensive verification coverage, including automation and scripting.
- Automate Digital Verification Processes: Automate Digital Verification processes and scripting to improve efficiency and reduce errors.
- Define and Manage Regression Infrastructure: Define, develop, and manage Regression infrastructure to ensure consistent and reliable verification results.
- Collaborate with Design Teams: Collaborate closely with Senior Digital and Analog Designers to develop VIP models and ensure seamless integration.
- Lead the Digital Verification Team: Lead the Digital Verification Team, overseeing multiple projects and supervising Digital Verification tasks across various projects.
- Review and Analyze Verification Results: Review and analyze Digital Verification Metrics and Results across projects to ensure comprehensive verification coverage.
- Design Top-Level Digital Verification Tests: Design top-level Digital Verification tests to ensure comprehensive verification coverage.
- Estimate and Plan Verification Tasks: Estimate, plan, and schedule Digital Verification tasks to meet tape-out deadlines.
- PhD/BS/MS in Electrical Engineering: Hold a PhD/BS/MS in Electrical Engineering with a focus on Digital Design/VLSI coursework.
- 10+ Years of ASIC Verification Experience: Have over 10 years of robust experience in ASIC Verification.
- Expertise in Power Management: Have expertise in power management DC-DC converters and control topologies (e.g., PWM control, constant-on-time control, voltage/current mode controls).
- Proficiency in Digital Verification Languages: Be proficient in Digital Verification Industry Languages (UVM, SystemVerilog) and Standards.
- Strong Skills in Constraint Random Tests: Have strong skills in Constraint Random Tests, SV Assertions, coverage metrics, analog and digital DV modeling, DV test plans, regression analysis, and reporting.
- Comprehensive Knowledge of ASIC Design Flow: Have comprehensive knowledge of the ASIC Digital Design Flow: Specification definition, RTL Verification, Synthesis, P&R, Gate-Level Verification, Power Estimation, ATPG Generation and Simulation, AMS Sims, etc.
- Proficient Use of Industry-Standard ASIC Tools: Be proficient in the use of industry-standard ASIC tools and flows (Digital Simulators, synthesis tools, DFT, LEC, STA, etc.).
- Excellent Scripting and Automation Skills: Have excellent scripting and automation skills using TCL, Python, or C/C++.
- Leadership and Communication Skills: Possess leadership capabilities to guide and mentor the Digital Verification Team and strong written and verbal communication skills with a collaborative team-oriented approach.
- Knowledge of Automotive Standards: Have knowledge or experience in automotive standards/FuSA, I2C, I3C, SPI, USB, PMBUS, I2S, CAN, LIN, Embedded MCU (ARM/RISC V) designs, and/or SoC development is advantageous.
- Proficiency in Chinese Communication: Proficiency in Chinese communication is highly desired.
