Digital Verification Engineer

hace 3 semanas

Barcelona, Barcelona, España Monolithic Power Systems A tiempo completo
Job Summary

A Principal Digital Verification Engineer will define and lead the development of the Digital Verification framework and infrastructure of complex digital and mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools.

Key Responsibilities
  • Develop and maintain a UVM and System Verilog based Digital Verification environment.
  • Define and standardize VIPs, develop and document them.
  • Integrate VIPs into the Project's Digital Verification environment.
  • Develop Digital Verification Metrics for RTL and Gate-Level Verification.
  • Define and develop Test Plans.
  • Implement Digital Verification Automation and Scripting.
  • Develop Regression's infrastructure, manage it.
  • Collaborate with Senior Digital and Analog Designers to develop VIP models.
  • Lead the Digital Verification Team.
  • Supervise Digital Verification Tasks of multiple projects.
  • Review Digital Verification Metrics and Results of multiple projects.
  • Design and develop Digital Verification Top-Level Tests.
  • Analyze and debug test results, code coverage and functional coverage.
  • Estimate, plan and schedule Digital Verification to meet tape-out dates.
Requirements
  • PhD/BS/MS in Electrical Engineering with emphasis in Digital Design/VLSI coursework.
  • 10+ years of strong experience in ASIC Verification.
  • Experience in power management DC-DC convertors + control topologies, such as PWM control, constant–on–time control, and voltage/current mode controls.
  • Proficient in Digital Verification Industry Languages (UVM, System Verilog) and Standards.
  • Proficient Level in DV skills and areas: Constraint random tests, SV assertions, coverage metrics, analog and digital DV modelling, DV test plans, regression analysis and reports, UVM DV Agents (Monitor, Driver, Scoreboard), etc.
  • Solid knowledge and experience working through the entire Digital Design Flow: Specification definition, RTL Verification, Synthesis, P&R, Gate-Level Verification, Power Estimation, ATPG Generation and Simulation, AMS Sims, etc.
  • Excellent Knowledge & Use of industry standard ASIC tools/flow for daily work: Digital Simulators, synthesis tools, DFT, LEC, STA, etc.
  • Excellent scripting and automation skills using TCL, Python or C/C++.
  • Leadership skills to technically guide the DV Team and mentor Jr. DV Designers.
  • Good written/verbal communication skills and strong team work/collaboration.
  • Knowledge/Experience with the following is a plus: automotive standards/FuSAI2C, I3C, SPI, USB, PMBUS, I2S, CAN, LINEmbedded MCU(ARM/RISC V) designs and/or SoC developmentAbility to communicate in Chinese highly desired.
Location
  • Barcelona, Spain
  • Portugal (Lisbon/Porto)
  • Netherlands (Enschede/Nijmegen)
  • Switzerland (Tolochenaz)

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