Digital Verification Engineer
hace 2 semanas
We are seeking a highly skilled Digital Verification Engineer to join our team at Monolithic Power Systems, Inc. (MPS). As a key member of our Automotive BMS Product Line, you will play a crucial role in developing the digital verification framework and infrastructure for complex digital and mixed-signal ICs.
Responsibilities:- Develop and maintain a UVM and System Verilog based digital verification environment
- Standardize, define, develop, and document Verification IP (VIP)
- Integrate VIPs into the digital verification environment
- Develop test plans to fully verify all digital requirements in project specifications
- Develop coverage metrics and test cases to fully cover all test plan items
- Script and automate digital verification tasks
- Manage regression infrastructure and debug test results, code coverage, and functional coverage
- Collaborate with Senior Digital and Analog Designers to develop VIP models and test cases
- Analyze and debug test results, code coverage, and functional coverage
- Estimate, plan, and schedule digital verification tasks to meet tape-out dates
- BSEE / MSEE or equivalent with emphasis in digital design / VLSI coursework
- 5+ years of experience in both RTL and gate-level verification
- Proficient in digital verification industry languages (UVM, System Verilog) and standards
- Strong knowledge in verification of low power and multiple power domain designs
- Experience with digital design, including RTL coding in System Verilog, digital synthesis, timing closure, and power estimation
- Good written / verbal communication skills and strong teamwork / collaboration
- Self-motivated with attention to detail and strong analytical and problem-solving skills
We offer a dynamic and innovative work environment with opportunities for growth and development. If you are a motivated and experienced Digital Verification Engineer looking for a new challenge, please submit your application.
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