Senior Digital Verification Engineer
hace 1 semana
Job Summary:
A Senior Digital Verification Engineer will lead the development of the Digital Verification framework and infrastructure of complex digital and mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools. The engineer will define and develop the Digital Verification environment, VIPs, and test plans, and will lead the Digital Verification Team.
Key Responsibilities:
Define and develop the Digital Verification environment using UVM and System Verilog.
Standardize, define, develop, and document VIPs.
Integrate VIPs into the Project's Digital Verification environment.
Define Digital Verification Metrics for RTL and Gate-Level Verification.
Develop Test Plans and lead the Digital Verification Automation and Scripting efforts.
Manage Regression's infrastructure and lead the Digital Verification Team.
Requirements:
PhD/BS/MS in Electrical Engineering with emphasis in Digital Design/VLSI coursework.
5+ years of strong experience in both RTL and Gate-Level Verification.
Proficient in Digital Verification Industry Languages (UVM, System Verilog) and Standards.
Excellent scripting and automation skills using TCL, Python, or C/C++.
Location:
Germany – Munich, Ottobrunn
Spain – Barcelona
Portugal – Lisbon / Porto
Netherlands – Enschede / Nijmegen
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