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Senior Digital Verification Engineer
hace 2 meses
A Senior Digital Verification Engineer will define and lead the development of the Digital Verification framework and infrastructure of complex digital and mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools.
Key Responsibilities- Develop and maintain a UVM and System Verilog based Digital Verification environment.
- Standardize, define, develop, and document VIPs.
- Integrate VIPs into the Project's Digital Verification environment.
- Define Digital Verification Metrics for RTL and Gate-Level Verification.
- Develop Test Plans and lead Digital Verification Automation and Scripting.
- Manage Regression's infrastructure and lead the Digital Verification Team.
- Close interaction with Senior Digital and Analog Designers to develop VIP models.
- PhD/BS/MS in Electrical Engineering with emphasis in Digital Design/VLSI coursework.
- 5+ years of strong experience in both RTL and Gate-Level Verification.
- Proficient in Digital Verification Industry Languages (UVM, System Verilog) and Standards.
- Excellent scripting and automation skills using TCL, Python or C/C++.
- Leadership skills to technically guide the DV Team and mentor Jr. DV Designers.
- Germany – Munich, Ottobrunn
- Spain – Barcelona
- Portugal – Lisbon / Porto
- Netherlands – Enschede / Nijmegen