Senior Digital Verification Engineer
hace 3 semanas
Epsilonr is seeking a highly skilled Digital Verification Engineer to lead the development of the digital verification framework and infrastructure for complex digital and mixed-signal ICs.
This role involves using cutting-edge technologies with industry-standard ASIC tools to design and verify products that may include power management, signal management, and mixed-signal functions.
Key Responsibilities:
- Define and develop UVM and System Verilog-based digital verification environments.
- Standardize, define, develop, and document verification IPs (VIPs).
- Integrate VIPs into the project's digital verification environment.
- Define digital verification metrics for RTL and gate-level verification.
- Develop and define test plans.
- Automate digital verification and create supporting scripts.
- Define, develop, and manage regression infrastructure.
- Collaborate closely with senior digital and analog designers to develop VIP models.
- Lead the digital verification team and supervise verification tasks across multiple projects.
- Review digital verification metrics and results for multiple projects.
- Define and design top-level digital verification tests.
- Analyze and debug test results, code coverage, and functional coverage.
- Estimate, plan, and schedule digital verification tasks to meet tape-out dates.
Requirements:
- PhD, BS, or MS in Electrical Engineering with a focus on Digital Design/VLSI coursework.
- 5+ years of strong experience in both RTL and gate-level verification.
- Proficient in digital verification industry languages (UVM, System Verilog) and standards.
Preferred Experience:
- Embedded design and/or firmware development.
- Knowledge of power management industry/applications.
- Familiarity with I2C, I3C, SPI, USB, PMBUS.
- Experience with GitLab.
Location:
This role can be based at either of the following office locations:
Barcelona, Spain
Porto/Lisbon, Portugal
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