Senior Digital Verification Engineer
hace 6 días
Job Summary:
A skilled Digital Verification Engineer will develop and lead the Digital Verification framework and infrastructure for complex ICs. The engineer will utilize leading-edge technologies and industry-standard ASIC tools to design and verify digital and mixed-signal ICs.
Key Responsibilities:
- Define and develop a Digital Verification environment using UVM and System Verilog.
- Standardize, develop, and document VIPs.
- Integrate VIPs into the project's Digital Verification environment.
- Define Digital Verification Metrics for RTL and Gate-Level Verification.
- Develop Test Plans and automate Digital Verification.
- Maintain Regression infrastructure and manage Digital Verification tasks.
Requirements:
- PhD/BS/MS in Electrical Engineering with a focus on Digital Design/VLSI coursework.
- 5+ years of experience in RTL and Gate-Level Verification.
- Proficiency in Digital Verification languages (UVM, System Verilog) and standards.
- Experience with industry-standard ASIC tools and flows.
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