Senior Digital Verification Engineer

hace 2 semanas

Barcelona, Barcelona, España Monolithic Power Systems A tiempo completo
Job Summary

A Senior Digital Verification Engineer will define and lead the development of the Digital Verification framework and infrastructure of complex digital and mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools. Products to be designed/verified may include power management, signal management and mixed signal functions.

Key Responsibilities
  • Develop and maintain a comprehensive Digital Verification environment using UVM and System Verilog.
  • Standardize, define, develop and document VIPs for digital verification.
  • Integrate VIPs into the project's digital verification environment.
  • Define digital verification metrics for RTL and gate-level verification.
  • Develop test plans and automate digital verification processes.
  • Manage regression infrastructure and lead the digital verification team.
  • Collaborate with senior designers to develop VIP models.
  • Lead and supervise digital verification tasks for multiple projects.
  • Analyze and debug test results, code coverage and functional coverage.
  • Estimate, plan and schedule digital verification activities to meet tape-out dates.
Requirements
  • PhD/BS/MS in Electrical Engineering with emphasis in digital design/VLSI coursework.
  • 5+ years of experience in RTL and gate-level verification.
  • Proficient in digital verification industry languages and standards.
  • Strong knowledge of digital verification skills and areas.
  • Excellent knowledge and experience working through the entire digital design flow.
  • Excellent scripting and automation skills using TCL, Python or C/C++.
  • Leadership skills to guide the DV team and mentor junior designers.
  • Good written/verbal communication skills and strong teamwork/collaboration.
Location
  • Germany - Munich, Ottobrunn
  • Spain - Barcelona
  • Portugal - Lisbon / Porto
  • Netherlands - Enschede / Nijmegen

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