Principal Digital Verification Engineer

hace 3 semanas

Barcelona, Barcelona, España Monolithic Power Systems A tiempo completo

Job Summary: A Principal Digital Verification Engineer will define and lead the development of the Digital Verification framework and infrastructure of complex digital and mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools. Products to be designed/verified may include power management, signal management and mixed signal functions. Key Responsibilities:

  • Define and develop UVM and System Verilog based Digital Verification environment.
  • Standardize, define, develop and document VIPs.
  • Integrate VIPs into the Project's Digital Verification environment.
  • Define Digital Verification Metrics for RTL and Gate-Level Verification.
  • Develop Test Plans and automate Digital Verification.
  • Manage Regression's infrastructure and develop Digital Verification Automation.
  • Collaborate with Senior Digital and Analog Designers to develop VIP models.
  • Lead the Digital Verification Team and supervise Digital Verification Tasks.
  • Analyze and debug test results, code coverage and functional coverage.
  • Estimate, plan and schedule Digital Verification to meet tape-out dates.
Qualifications:
  • PhD/BS/MS in Electrical Engineering with emphasis in Digital Design/VLSI coursework.
  • 10+ years of strong experience in ASIC Verification.
  • Experience in power management DC-DC convertors and control topologies.
  • Proficient in Digital Verification Industry Languages and Standards.
  • Excellent knowledge and experience working through the entire Digital Design Flow.
  • Leadership skills to guide the DV Team and mentor Jr. DV Designers.

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