Principal Digital Verification Engineer

hace 4 semanas

Barcelona, Barcelona, España Epsilonr A tiempo completo
Job Title: Principal Digital Verification Engineer

We are seeking a seasoned Principal Digital Verification Engineer to define and lead the development of advanced Digital Verification frameworks and infrastructure for complex digital and mixed-signal ICs using industry-leading ASIC tools.

Key Responsibilities:
  • Define and develop UVM and SystemVerilog-based Digital Verification environments.
  • Standardize, define, develop, and document Verification IPs (VIPs).
  • Integrate VIPs into the project's Digital Verification environment.
  • Define Digital Verification Metrics for RTL and Gate-Level Verification.
  • Develop and implement Test Plans for comprehensive verification coverage.
  • Automate Digital Verification processes and scripting.
  • Define, develop, and manage Regression infrastructure.
  • Collaborate closely with Senior Digital and Analog Designers to develop VIP models.
  • Lead the Digital Verification Team, overseeing multiple projects.
  • Supervise Digital Verification tasks across various projects.
  • Review Digital Verification Metrics and Results across projects.
  • Design top-level Digital Verification tests.
  • Analyze and debug test results, code coverage, and functional coverage.
  • Estimate, plan, and schedule Digital Verification tasks to meet tape-out deadlines.
Qualifications:
  • PhD/BS/MS in Electrical Engineering with a focus on Digital Design/VLSI coursework.
  • Over 10 years of robust experience in ASIC Verification.
  • Expertise in power management DC-DC converters and control topologies (e.g., PWM control, constant-on-time control, voltage/current mode controls).
  • Proficiency in Digital Verification Industry Languages (UVM, SystemVerilog) and Standards.
  • Strong skills in Constraint Random Tests, SV Assertions, coverage metrics, analog and digital DV modeling, DV test plans, regression analysis, and reporting.
  • Comprehensive knowledge of the ASIC Digital Design Flow: Specification definition, RTL Verification, Synthesis, P&R, Gate-Level Verification, Power Estimation, ATPG Generation and Simulation, AMS Sims, etc.
  • Proficient use of industry-standard ASIC tools and flows (Digital Simulators, synthesis tools, DFT, LEC, STA, etc.).
  • Excellent scripting and automation skills using TCL, Python, or C/C++.Leadership capabilities to guide and mentor the Digital Verification Team.
  • Strong written and verbal communication skills with a collaborative team-oriented approach.
  • Knowledge or experience in automotive standards/FuSA, I2C, I3C, SPI, USB, PMBUS, I2S, CAN, LIN, Embedded MCU (ARM/RISC V) designs, and/or SoC development is advantageous.
  • Proficiency in Chinese communication is highly desired.
Office Locations:
  • Barcelona, Spain
  • Enschede/Nijmegen, Netherlands
  • Porto/Lisbon, Portugal
  • Ottobrunn, Germany

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