Senior Verification Engineer

hace 3 semanas


Valencia, Valencia, España Analog Devices A tiempo completo
Job Summary

We are seeking a highly skilled Principal Engineer to join our Design Verification Engineering team at Analog Devices. As a key member of our team, you will be responsible for contributing to the verification of complex mixed-signal designs and sub-systems.

Key Responsibilities
  • Verification of complex mixed-signal designs and sub-systems
  • Good understanding of Mixed-Signal Industry Design Flow and Top-Down development methodology
  • Independent interpretation of analog circuit schematics
  • Analog Behavioral Models (SystemVerilog, Verilog-AMS, Wreal, UDNs, EEnet)
  • Validation of real number models vs SPICE models
  • Experience with SPICE simulations using industry simulators such as SPECTRE
  • Define test plans, tests, and verification methodology for block/chip-level verification of Mixed Signal Designs
  • Work with the design team in generating test-plans and closure of test and functional coverage
  • Continuous interaction with analog co-sim team in enabling top-level chip verification aspects
  • Contribute and influence the decisions on methodologies to be adopted for the verification
  • Technically mentor and guide junior verification engineers on SoC Verification
  • Support post-silicon verification activities of the products working with design, product evaluation and applications engineering team
  • Hands-On UVM at user level, pseudo and constrained random techniques, assertion-based verification techniques with System Verilog
Requirements
  • Bachelor's or master's degree in Engineering (Electronic Engineering) or equivalent
  • Excellent debugging and analytical skills
  • 10-15 years in ASIC design verification
  • Verification Planning tools (ePlanner, vManager)
  • Property Specification Language (PSL), SystemVerilog Assertions (SVA)
  • Proficient with Cadence Suite (Virtuoso IUS)
  • Scripting languages (Shell, TCL, PERL, Python) for bench automation


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