Senior Verification Engineer

hace 3 semanas


Valencia, Valencia, España Information Technology Association Galway A tiempo completo

Job Summary

As a Senior Verification Engineer at Analog Devices, you will be responsible for the verification of key digital blocks in differentiated mixed signal SOCs targeted for the consumer market. This includes testbench architecture, testplan and testbench development, functional coverage closure, and code coverage closure. You will use industry standard methodologies like UVM and constrained random approach to achieve verification goals. Additionally, you will explore and deploy techniques like Formal verification to achieve faster turnaround time on verification. Your expertise will be essential in debugging efficiently and clearly articulating gating issues to engineering leads. You will also integrate the block level testbench at SOC level and verify SOC integration, as well as participate in post-silicon activities such as silicon bring-up, evaluation support, and ATE pattern bring-up to take SoC into production.

Key Responsibilities

  • Develop UVM-based testbench infrastructure, functional cover point development, code coverage analysis/closure, and assertion development
  • Strong understanding and experience of Verilog and System Verilog
  • Excellent debug and problem-solving skills
  • Experience with both IP and SOC level verification
  • Self-motivated, diligent, and has an eye for detail
  • Knowledge in AHB/AXI/APB/SPMI protocols is desirable; experience in Power aware simulations or Formal Verification is a big plus
  • Experience in Verilog-AMS, analog behavior modelling is desirable
  • Understanding of Buck-Boost/Inverse Buck-Boost, LDOs, BG reference concepts in the form of projects or coursework is a plus
  • Proficiency in scripting languages and utilities including Makefile, Python, Perl, etc
  • Good written and verbal communication skills

Requirements
  • Electronic Engineering/Computer Engineering degree with 10+ years of progressive experience in Verification
  • Demonstrated experience in developing UVM-based testbench infrastructure, functional cover point development, code coverage analysis/closure, and assertion development
  • Strong understanding and experience of Verilog and System Verilog
  • Excellent debug and problem-solving skills
  • Experience with both IP and SOC level verification
  • Self-motivated, diligent, and has an eye for detail
  • Knowledge in AHB/AXI/APB/SPMI protocols is desirable; experience in Power aware simulations or Formal Verification is a big plus
  • Experience in Verilog-AMS, analog behavior modelling is desirable
  • Understanding of Buck-Boost/Inverse Buck-Boost, LDOs, BG reference concepts in the form of projects or coursework is a plus
  • Proficiency in scripting languages and utilities including Makefile, Python, Perl, etc
  • Good written and verbal communication skills

About Us
Analog Devices, Inc. is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. We combine analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $12 billion in FY23 and approximately 26,000 people globally working alongside 125,000 global customers, we ensure today's innovators stay Ahead of What's Possible. Learn more at www.Analog.Com and on LinkedIn and Twitter (X).

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