Senior Verification Engineer
hace 2 meses
About the Role:
We are seeking a highly skilled and experienced Senior Verification Engineer to join our Analog Design team. As a key member of our team, you will be responsible for developing and executing comprehensive verification plans, including testbench architecture, test cases, and coverage metrics. Your expertise in SystemVerilog, UVM, and other relevant verification languages and tools will be essential in ensuring the quality of our designs.
Responsibilities:
* Develop and execute comprehensive verification plans
* Create efficient and reusable testbench environments
* Generate directed and constrained random test cases
* Analyze coverage metrics and identify areas for improvement
* Diagnose and resolve design issues
* Provide guidance and mentorship to junior engineers
Qualifications:
* Bachelor's degree in Electrical Engineering, Computer Science, or a related field
* Minimum 7 years of experience in design verification
* Strong understanding of hardware design and verification methodologies
* Proficiency in SystemVerilog, UVM, and other relevant verification languages and tools
* Experience with coverage driven verification
Preferred Qualifications:
* Master's degree or higher in a related field
* Formal verification experience
* Experience with RISC-V systems
* C/C++ proficiency
* Knowledge of scripting languages
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