Digital Verification Expert for ASIC Design
hace 2 semanas
MaxLinear is seeking a highly skilled Senior Staff Digital Ic Design Verification Engineer to join our team in Paterna, Spain. This role offers a competitive salary package of approximately EUR 50,000 - 70,000 per annum.
About the RoleIn this position, you will be responsible for creating block-level and device test plans, developing testbenches, and executing test cases. You will work closely with mixed signal teams to integrate high-speed analog behavioral models and collaborate with the design team to assist with pre-silicon debug.
- You will create documentation for test plans and testbenches, assess functional code coverage reports, and augment test cases to meet defined test goals.
- You will prepare task lists, effort estimates, and commit to schedules while working under tight deadlines.
To be successful in this role, you must have:
- Knowledge of verification languages: UVM, System-Verilog.
- Experience with RTL design using Verilog and/or System Verilog.
- Strong logical and creative problem-solving skills with excellent analytical and debugging skills.
- Excellent written and verbal English communication skills and teamwork.
- Bachelor or Master of Science degree.
We offer a comprehensive compensation package including:
- Competitive Salary Package (EUR 50,000 - 70,000 per annum)
- Stock-based compensation
- Private Medical Insurance
- Life Insurance
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