Senior Verification Engineer

hace 2 semanas


Valencia, Valencia, España Robert Bosch Group A tiempo completo
Job Description:

As a Senior Verification Engineer at Robert Bosch Group, you will be responsible for developing accurate behavioral models for mixed-signal circuits. Your expertise will be utilized to verify the performance and accuracy of these models against circuit-level simulations and measurements. You will collaborate closely with system architects and analog/digital designers to understand circuit specifications, design intent, and performance requirements. Your role will also involve developing mixed signal verification strategies for state-of-the-art SoCs containing high speed digital circuits and sensitive analog/RF circuits. Additionally, you will implement verification plans, track their coverage, and develop and run system simulations to verify the design, analyze performance, power and timing, and uncover bugs. You will also replicate root causes and debug issues in the pre-silicon environment, find and implement corrective measures to resolve failing tests, and maintain and improve existing functional verification infrastructure and methodology. Furthermore, you will implement/maintain post processing scripts for assessing system performance and develop tools for automated generation of verification reports and regression management.

Qualifications:

You should possess a Masters or Bachelor's degree in Electrical/Electronics/Computer Engineering, with at least 5 years of relevant experience in the industry. You should have experience in developing high quality validation plans, collecting and analyzing test results, and debugging failures to RTL/gate/schematic level. Strong problem-solving and teamwork skills, and strong verbal and written communication skills are essential. You should be able to produce results in a challenging, fast-paced, multi-site, multi-group environment. Good working knowledge of Verilog/SystemVerilog is a must, as well as good working knowledge of UVM. Experience in setting up, running, and debugging Gate Level simulations is also required. Work experience with at least one other verification aspect like System modeling, Formal verification, etc. would be an added advantage. Proficiency in scripting languages and utilities including Make, Python, etc. will be a bonus.

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