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Senior Digital Verification Engineer
hace 2 meses
Job Summary:
A Senior Digital Verification Engineer will define and lead the development of the Digital Verification framework and infrastructure of complex digital and mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools. Products to be designed/verified may include power management, signal management and mixed signal functions. Monolithic Power Systems products include: switching regulators, sensors, motor control, display drivers, audio amplifiers and power management ICs for fast-growing portable and non-portable markets such as notebooks, cell phones, telecom, digital camera, automobile and network equipment.
Key Responsibilities:
- Develop and maintain a comprehensive Digital Verification environment using UVM and System Verilog.
- Standardize, define, develop and document VIPs (Virtual Integration Protocols) to ensure seamless integration with the project's Digital Verification environment.
- Define and implement VIP integration into the project's Digital Verification environment.
- Develop and maintain Digital Verification metrics for RTL and Gate-Level Verification to ensure high-quality designs.
- Collaborate with cross-functional teams to develop and implement Test Plans.
- Design and implement Digital Verification automation and scripting to streamline the verification process.
- Develop and manage Regression infrastructure to ensure efficient and effective testing.
- Work closely with Senior Digital and Analog Designers to develop VIP models.
- Lead and supervise Digital Verification tasks across multiple projects.
- Review and analyze Digital Verification metrics and results across multiple projects.
- Develop and design Digital Verification Top-Level Tests to ensure comprehensive coverage.
- Analyze and debug test results, code coverage and functional coverage to ensure high-quality designs.
- Develop and maintain Digital Verification estimation, planning and scheduling to meet project deadlines.
Requirements:
A PhD/BS/MS in Electrical Engineering with emphasis in Digital Design/VLSI coursework is required. 5+ years of strong experience in both RTL and Gate-Level Verification is necessary. Proficiency in Digital Verification Industry Languages (UVM, System Verilog) and Standards is required. Proficiency in DV skills and areas: Constraint random tests, SV assertions, coverage metrics, analog and digital DV modeling, DV test plans, regression analysis and reports, UVM DV Agents (Monitor, Driver, Scoreboard), etc. is necessary. Solid knowledge and experience working through the entire Digital Design Flow: Specification definition, RTL Verification, Synthesis, P&R, Gate-Level Verification, Power Estimation, ATPG Generation and Simulation, AMS Sims, etc. is required. Excellent Knowledge & Use of industry standard ASIC tools/flow for daily work: Digital Simulators, synthesis tools, DFT, LEC, STA, etc. is necessary. Excellent scripting and automation skills using TCL, Python or C/C++ is required. Leadership skills to technically guide the DV Team and mentor Jr. DV Designers is necessary. Good written/verbal communication skills and strong team work/collaboration is required. Knowledge/Experience with the following is a plus: Embedded designs and/or firmware development Knowledge of power management industry/applications I2C, I3C, SPI, USB, PMBUS GitLab.
Location:
Monolithic Power Systems has multiple locations worldwide.
