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Senior Digital Verification Engineer

hace 2 meses

Barcelona, Barcelona, España Monolithic Power Systems A tiempo completo

**Job Summary**

A Senior Digital Verification Engineer will define and lead the development of the Digital Verification framework and infrastructure of complex digital and mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools. Products to be designed/verified may include power management, signal management and mixed signal functions.

**Key Responsibilities**

  • Define and develop a UVM and System Verilog based Digital Verification environment.
  • Standardize, define, develop and document VIPs.
  • Integrate VIPs into the Project's Digital Verification environment.
  • Define Digital Verification Metrics for RTL and Gate-Level Verification.
  • Develop Test Plans and automate Digital Verification processes.
  • Manage Regression infrastructure and results.
  • Collaborate with Senior Digital and Analog Designers to develop VIP models.
  • Lead the Digital Verification Team and supervise tasks.
  • Analyze and debug test results, code coverage and functional coverage.
  • Estimate, plan and schedule Digital Verification tasks to meet tape-out dates.

**Requirements**

  • PhD/BS/MS in Electrical Engineering with emphasis in Digital Design/VLSI coursework.
  • 5+ years of strong experience in both RTL and Gate-Level Verification.
  • Proficient in Digital Verification Industry Languages (UVM, System Verilog) and Standards.
  • Excellent knowledge and experience working through the entire Digital Design Flow.
  • Strong scripting and automation skills using TCL, Python or C/C++.
  • Leadership skills to guide the DV Team and mentor Jr. DV Designers.

**Preferred Qualifications**

  • Embedded designs and/or firmware development experience.
  • Knowledge of power management industry/applications.