Junior Research Engineer

hace 3 meses


Barcelona, España Barcelona Supercomputing Center (BSC) A tiempo completo

**Job Reference**:

- 523_24_CS_SPI_RE1**Position**:

- Junior Research Engineer (RE1)**Closing Date**:

- Monday, 16 September, 2024**Reference**: 523_24_CS_SPI_RE1**Job title**: Junior Research Engineer (RE1)**About BSC**
- The Barcelona Supercomputing Center - Centro Nacional de Supercomputación (BSC-CNS) is the leading supercomputing center in Spain. It houses MareNostrum, one of the most powerful supercomputers in Europe, was a founding and hosting member of the former European HPC infrastructure PRACE (Partnership for Advanced Computing in Europe), and is now hosting entity for EuroHPC JU, the Joint Undertaking that leads large-scale investments and HPC provision in Europe. The mission of BSC is to research, develop and manage information technologies in order to facilitate scientific progress. BSC combines HPC service provision and R&D into both computer and computational science (life, earth and engineering sciences) under one roof, and currently has over 1000 staff from 60 countries.

Look at the BSC experience:
BSC-CNS YouTube Channel
Let's stay connected with BSC Folks

We promote Equity, Diversity and Inclusion, fostering an environment where each and every one of us is appreciated for who we are, regardless of our differences.**Context And Mission**
- Applications are invited for one junior research engineer in ASIC physical design at the Barcelona Supercomputing Center (BSC-CNS). We are offering a position in the context of multiple industry-funded projects to perform and lead tasks in integrated circuit design.**Key Duties**
- Synthesis of complex ASIC RTL designs
- ASIC area, timing and power estimation

**Requirements**:

- Education
- Master in Electronic Engineering and related fields or last year master students with at least 60 ECTS of master courses.
- Essential Knowledge and Professional Experience
- ASIC synthesis and place and route EDA tools (Cadence or Synopsys)
- HDL languages (Verilog, Systemverilog or VHDL) for synthesis
- Competences
- Ability to take initiative, prioritize and work under set deadlines.
- Ability to work independently and in a team.

**Conditions**
- The position will be located at BSC within the Computer Sciences Department
- We offer a full-time contract (37.5h/week), a good working environment, a highly stimulating environment with state-of-the-art infrastructure, flexible working hours, extensive training plan, restaurant tickets, private health insurance, support to the relocation procedures
- Duration: Open-ended contract due to technical and scientific activities linked to the project and budget duration
- Holidays: 23 paid vacation days plus 24th and 31st of December per our collective agreement
- Starting date: 1/10/2024

**Applications procedure and process**
- A full CV in English including contact details
- A Cover Letter with a statement of interest in English, including two contacts for further references - Applications without this document will not be considered

At BSC we are seeking continuous improvement in our recruitment processes, for any suggestions or feedback/complaints about our Recruitment Processes, please contact recruitment [at] bsc [dot] es.

For more information follow this link

**Deadline**OTM-R principles for selection processes**

BSC-CNS is an equal opportunity employer committed to diversity and inclusion. We are pleased to consider all qualified applicants for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or any other basis protected by applicable state or local law.
For more information follow this link



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