Embedded RTL Engineer – ASIC/FPGA Innovation

Hace 3 días

Madrid, Comunidad de Madrid, España GMV Spain Jornada completa 50.000 € - 75.000 € Por obra

GMV Spain is expanding its GNSS‑User Segment Navigation team to migrate an architecture from Xilinx MPSoC/FPGA to an ASIC solution. The role emphasizes RTL development, IP integration, and extensive ASIC flow activities in a cutting-edge hardware environment.

We value candidates with hands-on experience in digital hardware programming, SystemVerilog-based verification, and familiarity with industry tools (Synopsys, Cadence, Vivado). Hybrid working model and relocation support offered.