Digital Design Verification Engineer

hace 1 semana

Paterna, Valencia, España Photonic Sensors & Algorithms A tiempo completo
Everything we do is designed to challenge the limits of imaging and sensing technologies. We thrive on excellence in execution while having fun pushing the boundaries of what an image can express.

We offer a permanent contract with a competitive salary and career opportunity in a growing company with global coverage and ambition.

There's still a lot of work to be done. We need best in class optical designers, software, parallel computing, heterogeneous computing and digital image processing experts.

We'd like to hear from you If you have experience or a PhD in one of the following fields:
Computer Science, Telecommunication Engineering, Parallel Computing, Electronic Engineering, Physics, Mathematics.


Digital Design Verification Engineer to help developing an innovative low-power consumption ASIC to obtain high-quality depth maps and images by processing real-time video frames captured by apiCAM, our leading, state-of the-art 3D camera.


apiCAM offers simultaneously 2D and 3D with a single lens, currently at 30 fps (frames per second), higher in the future.

apiCAM is already available in commercial products for Medical Imaging, Robotics, Industry 4.0 and aims to be in the next generation of XR-glasses, Tablets, PCs and Smartphones.

You will join our Algorithms team, specifically the Digital Verification Group for our state-of-the-art depth and imaging algorithms. This team is part of our R&D Department with experts in Physical-Optics, Image-Processing, Algorithms, Software and Industrial Automation.

_Responsibilities_

  • Contribute to the tasks defining low power consumption but extremely efficient digital designs.
  • Implement testbenches to ensure that the digital designs comply to specifications are robust and interact correctly with other IPblocks. Will use Xilinx development tools for FPGAs and in the future Formal Verification tools for ASICs.
  • Collaborate with digital design engineers to redefine and optimize digital IPblocks.

_Requirements_

  • Bachelor and/or Master degree in Telecommunication, Electronics, computer science or related fields.
  • HDL-Hardware Description Languages (Verilog or VHDL) and integration of IPblocks. Development of testbenches using SystemVerilog and UVM methodologies for the verification of complex digital designs.
  • Version control software such as Git or SVN.
  • Understanding of signal processing algorithms in Matlab Python and/or C++.
  • Motivated, willing to work in a team and to face big challenges such as the design, verification, and manufacturing of a complex ASIC from the very beginning.

_Desirable_

  • Knowledge of basic FPGA architectures and modes of operation.
  • State machines.
  • Design of parametric testbenches and test vectors for complex digital designs.
  • Finite precision modelling in Matlab or others.

_We offer_

  • Competitive salary according to your experience.
  • Flexible working hours (12 teleworking days per week).
  • Flexible compensation plan (restaurant tickets, transport, childcare, health insurance ).
  • Professional career plan within the company. Lifelong learning.
  • Dynamic startup environment.
  • Fix contract and professional stability within a demanding but friendly working environment.
  • Join us_


We create disruptive technologies, we aim for global leadership in our disciplines, we enjoy what we do, we live innovation every day, and we invite you to explore the opportunities offered.

Come and discover it

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