Design Verification Engineer

Hireroo Ltd in Barcelona seeks a Design Verification Engineer to drive gate-level simulation, hardware emulation and timing verification for advanced ASIC/SoC designs. You will collaborate with RTL, DFT, physical design and firmware teams to validate synthesized designs before silicon.Mid to senior level, you will optimize simulation performance, automate...

We are currently looking for an experienced Lead Design Verification Engineer to join an innovative semiconductor business developing advanced AI SoC and high-performance silicon technologies. This is an exciting opportunity for a senior verification specialist to take technical ownership of complex subsystem and IP-level verification, focusing on...

We are looking for a Design Verification Engineer to support gate-level simulation (GLS) and hardware emulation activities for our AI chip design and verification teams. This is a hands-on role requiring close collaboration with RTL design, DFT, physical design, and firmware teams. Set up, run, and debug gate-level simulations (GLS) for functional, timing...

Job Description Our partner is looking for a Design Verification Engineer to support gate level simulation and hardware emulation for advanced semiconductor designs. The role focuses on validating synthesized designs, identifying timing and functional issues, and supporting hardware emulation before silicon production. You will collaborate with RTL,...

We are looking for a Design Verification Engineer to support gate-level simulation (GLS) and hardware emulation activities for our AI chip design and verification teams. In this role, you will help ensure silicon correctness by validating post-synthesis netlists, debugging timing and reset issues, and enabling large-scale emulation of SoC designs prior to...

Job DescriptionSiga leyendo para descubrir lo que necesitará para tener éxito en este puesto, incluyendo habilidades, cualificaciones y experiencia.Our partner is looking for a Design Verification Engineer to support gate level simulation and hardware emulation for advanced semiconductor designs. The role focuses on validating synthesized designs,...

Semidynamics in Barcelona is seeking a Design Verification Engineer to support gate-level simulation and hardware emulation for our AI chip design teams. You will validate post-synthesis netlists, debug timing and reset issues, and enable large-scale emulation of SoC designs prior to tapeout. This hands-on role requires close collaboration with RTL design,...

Job Description Our partner is looking for a Lead Design Verification Engineer to lead functional verification of high speed interface protocol blocks at IP and subsystem level. The role combines hands on verification ownership with technical leadership, covering UVM environments, protocol compliance, debug, coverage closure and coordination with RTL,...

Hireroo Ltd in Barcelona seeks a Design Verification Engineer to drive gate-level simulation, hardware emulation and timing verification for advanced ASIC/SoC designs. You will collaborate with RTL, DFT, physical design and firmware teams to validate synthesized designs before silicon. Mid to senior level, you will optimize simulation performance, automate...