Senior Analog

Teledyne Sevilla seeks a seasoned IC Design Engineer to contribute to analog and mixed-signal system development, including transistor-level design and verification.
You will define architectures, model signals with HDL, and validate silicon through comprehensive simulations.Requirements include 3+ years in analog IC design with CMOS tech, plus 2+ years using Cadence tools like Virtuoso/Spectre/PVS/Calibre.
Hybrid work in Seville, Spain is offered.
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