Senior Gls

Seynamics in Barcelona, Spain seeks a Design Verification Engineer to support gate-level simulations and hardware emulation for AI chip verification teams.
You will validate post-synthesis netlists, debug timing and reset issues, and enable large-scale emulation of SoCs prior to tapeout.This hands-on role requires close collaboration with RTL, DFT, physical design, and firmware teams.
Senior position with emphasis on GLS and emulation, testbench development, and regression management.
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