PICs@ICFO Strategic Initiative: Postdoctoral Researcher in TGV Metallization and Seed-Layer Processes

ICFO
- The Institute of Photonic Sciences Organisation/Company ICFO
- The Institute of Photonic Sciences Research Field Chemistry » Other Engineering » Chemical engineering Engineering » Electrical engineering Physics » Other Researcher Profile Recognised Researcher (R2) Positions Research Support Positions Application Deadline 29 Oct 2026
- 00:00 (Europe/Madrid) Country Spain Type of Contract Temporary Job Status Full-time Offer Starting Date 16 Oct 2026 Is the job funded through the EU Research Framework Programme? Not funded by a EU programme Is the Job related to staff position within a Research Infrastructure? No Offer Description As part of the PICs@ICFO Strategic Initiative, ICFO coordinates PIXEurope, a flagship Pilot Line funded under the European Chips JU program, focused on Advanced Photonic Integrated Circuits (PICs) through which ICFO is advancing frontier technologies, including optical interposers for Co-packaged optics for next-generation optoelectronic and photonic devices. To strengthen this initiative, ICFO is seeking a highly motivated Engineer/Scientist with strong expertise in thin-film deposition and metallization of high-aspect-ratio Through-Glass Vias (TGVs). Position Overview:,

We offer
a post-doctoral position to a scientist with hands‑on experience in thin‑film deposition, surface preparation, and metallization for semiconductor, MEMS, or advanced‑packaging applications. The successful candidate will develop, optimize, and scale reliable adhesion, barrier, and conductive seed layers inside high‑aspect‑ratio glass vias, ensuring continuity and compatibility with subsequent copper plating and interconnection processes.

Key Responsibilities
, The selected candidate will be expected to:
* Develop and optimize seed‑layer deposition processes for high‑aspect‑ratio Through‑Glass Vias
* Develop substrate cleaning, glass‑surface activation, and adhesion‑promotion processes
* Develop adhesion, barrier, and conductive seed stacks such as Ti/Cu, Cr/Cu, TiW/Cu, and related systems
* Optimize sputtering, evaporation, electroless, ALD or CVD‑assisted, and hybrid deposition approaches
* Achieve continuous and conformal seed coverage along via entrances, sidewalls, and exits
* Characterize thickness, morphology, resistivity, adhesion, continuity, and wafer‑level uniformity
* Identify and mitigate shadowing, seed discontinuity, oxidation, delamination, and cracking
* Coordinate with the laser and glass team to align via geometry and surface condition with seeding, plating, and interconnection requirements This position will report to the Prof. Dr. Valerio Pruneri, Director of the European Chips JU Pilot Line PIXEurope. PIXEurope is co‑funded by the Chips Joint Undertaking and national funding authorities of the Participating States, Spain, Ireland, The Netherlands, Finland, Belgium, Portugal, Poland, Austria, France, Italy, United Kingdom. In particular, it is co‑funded by Spain through the Ministry for Digital Transformation and Civil Service under reference CJU-010000-2025-0005, as part of the Recovery, Transformation and Resilience Plan (PRTR). Applicants must hold a PhD in materials science, chemistry, chemical engineering, electrical engineering, microelectronics, physics, microengineering, or related fields, or equivalent research experience. Candidates should demonstrate expertise in the following areas (not all mandatory, but strongly preferred):
* Thin‑film deposition by sputtering, evaporation, ALD, CVD, or electroless methods
* Metallization processes for semiconductor, MEMS, microfabrication, or advanced‑packaging applications
* Surface preparation, activation, and surface chemistry of glass or dielectric materials
* Metal‑to‑dielectric adhesion and adhesion/barrier/seed‑layer material systems
* Metallization or coating of high‑aspect‑ratio three‑dimensional structures
* Redistribution layer patterning and fabrication
* Electrical and structural characterization of thin films and interconnects
* Cleanroom processes, safety procedures, and fabrication protocols
* Process optimization, reproducibility, failure analysis, and wafer‑level uniformity Desired (but not required):
* Direct experience with Through‑Glass Via or Through‑Silicon Via metallization
* Experience with FIB/SEM cross‑sections, X‑ray inspection, four‑point‑probe measurements, or via‑resistance testing
* Experience with reliability testing, thermomechanical stress, process scale‑up, or wafer‑level packaging
* Experience with glass surface processing will be evaluated as a strong asset
* Experience with electroless deposition, ALD‑assisted seeding, or electroplating Languages ENGLISH Level Excellent Research Field Engineering » Electrical engineeringEngineering » Chemical engineeringPhysics » OtherChemistry » Other Additional Information

What We Offer
* Access to state‑of‑the‑art microfabrication and characterization facilities
* A dynamic and interdisciplinary research environment
* Opportunities to work on high‑impact pro