Principal Rfic Design Engineer
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OverviewIn this principal role, you lead RFIC/analog/mixed-signal design initiatives from architecture to production, shaping architecture decisions and design methodology.
You will own critical blocks end-to-end, drive verification and silicon bring-up, and mentor the RFIC team.
The position emphasizes cross-functional leadership across RF, analog, digital, and packaging domains to deliver high-volume, high-performance ICs.
A strong impact on product quality and manufacturing readiness awaits.
Compensaciones / BeneficiosCompetitive Salary Package
Stock-based compensation
Private Medical Insurance
Life Insurance
ResponsabilidadesLead architecture, design, simulation, and verification of RF, analog baseband, data-converter, SerDes, and mixed-signal circuits
Own critical RFIC blocks from spec to tapeout, characterization, and production
Lead circuits such as LNAs, PAs, mixers, VGAs, RF front ends, ADCs/DACs, PLLs, VCOs, clock generation, biasing, and power-management
Translate system requirements into circuit specs, architectures, and verification plans across PVT, noise, linearity, and reliability
Lead RFIC top-level integration and sign-off across RF/analog/digital/package/power with attention to supply coupling and signal integrity
Collaborate with layout on RF-aware layout, parasitics, EM, extraction, and post-layout verification
Define characterization, calibration, ATE, and production-test strategies for high-volume manufacturing
Lead silicon investigations, diagnose root causes, and drive resolution during bring-up and productization
Provide technical guidance and mentorship through design reviews and cross-functional alignment
Requisitos principales10+ years in RFIC or analog/mixed-signal IC design with production silicon ownership
Strong RF/analog fundamentals: noise, linearity, matching, stability, device modeling, process variation
Hands-on design across RF/SerDes/analog baseband blocks (LNAs, PAs, mixers, ADCs/DACs, PLLs, VCOs, etc.)
Cadence Virtuoso/Spectre or equivalent, plus verification methods (S-parameters, PSS/PAC/PNOISE, transient/noise, baseband performance analysis)
Layout-dependent effects, parasitic extraction, EM, and post-layout verification
Experience in high-volume integrated products in advanced CMOS for wireless, data, SerDes, or similar domains
Understanding of on-chip LDOs, biasing, calibration, packaging interactions, ATE, and high-volume manufacturing
Strong analytical, debugging, decision-making, and cross-disciplinary communication skills
Fluent English (written and spoken)
leadership and mentorship
cross-functional collaboration
technical communication
RFIC design
Analog/digital mixed-signal design
LNA/PA/Mixer/VGA/ADC/DAC design
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