Senior Formal Verification Engineer
Hace 5 días
Eixample, Cataluña, España
Openchip & Software Technologies
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Openchip & Software Technologies S.
L. is seeking a Senior Formal Verification Engineer to lead the formal verification strategy across our SoC platforms. You will work with system architects to establish verification environments, write SystemVerilog assertions, and guide the use of formal methods to improve IP and chip-level verification efficiency. You will design verification methodologies, create multi-level test plans, analyze coverage, and participate in regression frameworks and project
L. is seeking a Senior Formal Verification Engineer to lead the formal verification strategy across our SoC platforms. You will work with system architects to establish verification environments, write SystemVerilog assertions, and guide the use of formal methods to improve IP and chip-level verification efficiency. You will design verification methodologies, create multi-level test plans, analyze coverage, and participate in regression frameworks and project