Lead Physical Design Engineer – RISC-V

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Meet the team The Physical Design team within Cisco Silicon One owns backend methodology and flow development from RTL to...

IC Resources is working with a client in Barcelona seeking an experienced Physical Design Engineer to lead the team on complex RISC-V IP projects. You will drive the full PD flow and mentor engineers as the business grows.The role offers opportunities for career progression in a fast-paced environment, with Barcelona-based team involvement and exposure to...

I have an exciting new opportunity with a client looking to grow their team in Barcelona. They are looking for an experienced Physical Design Engineer to Lead the team. This is a fantastic opportunity to work on complex projects and RISC-V IP. They have some huge growth plans for the next few years, so now is a great to join to watch the business grow, and...

I have an exciting new opportunity with a client looking to grow their team in Barcelona, they are looking for an experience Physical Design Engineer to Lead the team. This is a fantastic opportunity to work on complex projects and RISC-V IP. They have some huge growth plans for the next few years so now is a great to join to watch the business grow and...

Aion Silicon Ltd in Barcelona, Spain seeks a Senior Methodology Engineer to lead RTL-to-Signoff physical design automation and quality systems for complex So C/ASIC projects. You will build scalable automation frameworks and improve silicon delivery across advanced nodes. The role combines hands-on EDA tool experience (Cadence Innovus, Tempus, Voltus,...

Aion Silicon Ltd seeks a seasoned Principal Engineer for SoC Physical Design to lead complex ASIC/SoC implementations from architecture to tape-out. You will drive full-chip physical design, floorplanning, power/clock planning, PMU strategies, and signoff, collaborating across Architecture, RTL, Verification, DFT, STA, Packaging, and Silicon Validation...

We are seeking a highly motivated and experienced Principal Engineer - SoC Physical Design or Chip-Level Expert to lead the implementation of complex ASIC/SoC designs from architecture definition through successful tape-out. The ideal candidate will have deep expertise in full-chip physical design, SoC integration, advanced-node implementation, and...

Senior Verification Engineer – Drive Quality in Next‑Gen RISC‑V CPUs (UVM/SystemVerilog)OverviewAt Akuaro, we are proudly leading the recruitment process for our partner — a European deep-tech company redefining what’s possible in high-performance computing and digital infrastructure. Specialized in cutting-edge RISC-V systems and backed by major...

I have an exciting new opportunity with a client looking to grow the team in Barcelona, they are looking for Physical Design Engineers with all levels of experience to come and join the team. This is a fantastic opportunity to work on complex projects and RISC-V IP. They have some huge growth plans for the next few years so now is a great to join to watch...