Senior SoC Verification Manager
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As Senior SoC Verification Manager, you will own the verification strategy for a multi-core, cache-coherent AI processor SoC and drive it from verification plan through tape-out. You will lead and mentor a small team of verification leads across CPU cores, cache, and interconnects, shaping the verification approach in close collaboration with architecture and RTL. You will exploit SystemVerilog/UVM, verification automation, and various simulation/emulation tools to ensure reliable, scalable validation. This role offers the opportunity to influence chip architecture and memory performance while working in a hybrid Barcelona-based setting with international sponsorship.
Compensaciones / Beneficios- visa sponsorship
- relocation support
- hybrid working model
- career development opportunities
- competitive compensation package
- international opportunities
- Define verification strategies, plans, methodologies and coverage targets
- Lead verification of a 4-core coherent SoC through tape-out sign-off
- Manage and mentor 3–4 verification leads across CPU cores, L2 cache, interconnects and subsystems
- Drive functional verification using SystemVerilog and UVM
- Oversee simulation, emulation, regression infrastructure and verification automation
- Collaborate with architecture and RTL design teams to influence technical decisions
- Manage verification schedules, resources, risks and team development
- 12+ years of ASIC/SoC design verification experience
- Expert knowledge of SystemVerilog and UVM
- Proven experience leading verification engineers or technical teams
- Strong experience verifying cache-coherent multi-core systems or subsystems
- Experience driving verification planning, coverage closure and tape-out sign-off
- Knowledge of AXI, CHI and industry-standard simulation tools (VCS, Questa or Xcelium)
- Experience with RISC-V, CPU verification, AI accelerators, formal verification or emulation (advantageous)
- people leadership
- cross-functional collaboration
- mentoring and team development
- SystemVerilog
- UVM
- AXI
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