Senior Engineer, Design Verification

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at The Group The charter of ADI’s CSS team is to lead the market in selected technology domains with highly differentiated sensing and signal processing solutions. Today these technology areas include Capacitive Sensing, Optical Image Stabilization and Audio that drive growth in our portable and non-portable consumer business. Responsibilities Verification of complex designs and sub-systems using leading edge verification methodologies. Contribute and influence the decisions on methodologies to be adopted for the verification. Technically mentor and guide junior verification engineers on SoC Verification. Architect the testbench and develop in UVM or Formal based verification approaches. Integrate the block testbench in chip-level UVM environment and verify integration. Define test plans, tests, and verification methodology for block / chip-level verification. Work with the design team in generating test-plans and closure of code and functional coverage. Continuous interaction with analog co-sim and firmware team in enabling top-level chip verification aspects. Support post-silicon verification activities of the products working with design, product evaluation and applications engineering team. Qualifications Bachelor's or master’s degree, in Engineering (Electronic Engineering) or equivalent. 5+ years ASIC design, verification, or related work experience. Additional Preferred Qualifications Proficient in developing unit and SoC level test benches using VMM/OVM/UVM. Strong knowledge of test-plan generation, coverage analysis transaction level modeling, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog. Experience working with Cortex-M series-based processors. Experience in Gate Level Simulation (GLS) verification flow for SoC verification. Experience of pre and post-silicon verification test flow and automated test benches. Verilog, C/C++, System C, Java, TCL/Perl/Python/shell-scripting. Building and leading verification teams is a plus. RTL design/front-end design/FPGA flow (Intel Cyclone VE / Xilinx ZCU104) experience. Formal verification methodology. Strong interpersonal, teamwork and communication skills are required. Be self-motivated and enthusiastic. For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except U.S. Citizens, U.S. Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days #J-18808-Ljbffr