Digital Verification Engineer: Power Electronics and Mixed-Signal ICs

hace 5 horas


Barcelona, Barcelona, España Monolithic Power Systems Inc. A tiempo completo

Company Overview: Monolithic Power Systems, Inc. is a leading company in the Semiconductor industry, recognized for its innovation and commitment to sustainability. We are technical leaders in Integrated Power Semiconductors and Systems Power delivery architectures.

Job Description: As a Digital Verification Engineer, you will work on the development of the Digital Verification framework and infrastructure for complex digital and mixed-signal ICs using advanced technologies with industry-standard ASIC tools. Your products may include power management, signal management, and mixed-signal functions.

Essential Responsibilities:

  • Develop and maintain a UVM and System Verilog-based Digital Verification environment.
  • Standardize, define, develop, and document VIPs.
  • Integrate VIPs into the project's Digital Verification environment.
  • Define Digital Verification Metrics for RTL and Gate-Level Verification.
  • Create Test Plans and develop Digital Verification Automation and Scripting.
  • Manage Regression's infrastructure definition, development, and management.
  • Collaborate closely with Senior Digital and Analog Designers to develop VIP models.
  • Analyze and debug test results, code coverage, and functional coverage.
  • Assist in digital verification estimation, planning, and scheduling to meet tape-out dates.

Requirements:

  • PhD/BS/MS in Electrical Engineering with emphasis in Digital Design/VLSI coursework.
  • 3+ years of experience in both RTL and Gate-Level Verification.
  • Proficiency in Digital Verification Industry Languages (UVM, System Verilog) and Standards.
  • Familiarity with DV skills and areas: Constraint random tests, SV assertions, coverage metrics, analog and digital DV modeling, DV test plans, regression analysis and reports, UVM DV Agents (Monitor, Driver, Scoreboard), etc.
  • Knowledge and experience working through the entire Digital Design Flow: Specification definition, RTL Verification, Synthesis, P&R, Gate-Level Verification, Power Estimation, ATPG Generation and Simulation, AMS Sims, etc.
  • Excellent scripting and automation skills using Python and C/C++ (TCL is a plus).

Location: Lisbon or Porto, Portugal.

Salary: $120,000 - $150,000 per year, depending on experience.



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