Digital Design Architect for Mixed-Signal ICs
hace 2 días
Epsilonr is seeking a highly skilled Digital Design Architect for Mixed-Signal ICs to join our team of experienced design engineers in one of our European offices. This full-time position requires on-site presence with no remote option available.
About the RoleThis senior-level position involves overseeing all aspects of physical design and implementation, contributing to the establishment of physical design methodologies and workflow automation. As a key member of the design development team, you will focus on digital design implementation and verification of mixed-signal ICs using standard EDA tools.
Key Responsibilities- Lead physical design, development, and verification of digital/mixed-signal ICs.
- Manage chip and block floorplan/implementation, power and clock distribution, chip assembly, Place & Route (P&R), Static Timing Analysis (STA), and Layout vs. Schematic (LVS)/Design Rule Check (DRC) closure.
- Collaborate closely with the digital/analog design team for physical implementation and integration of custom analog blocks/interfaces/IPs.
- Contribute to building an automated RTL-to-PNR environment using high-level languages and DevOps-like services.
We are looking for a highly qualified individual with:
- An advanced degree in Electrical Engineering, Computer Science, or equivalent.
- Preferred 3-5 years of experience in Physical Digital Design.
- Preferred 2+ years of experience in ASIC design, verification, or related work.
- Strong written and verbal communication skills in English, with demonstrated ability to collaborate effectively in a team environment.
- Ability to work independently, follow design specifications, and execute tasks to meet project milestones with high quality.
- Solid knowledge of the ASIC development process and digital design techniques.
- Proficiency in programming, scripting, and automation languages such as Perl, TCL, and Unix.
- Technical expertise in Verilog/System Verilog coding.
- Synthesis, Logical Equivalence Checking (LEC), Clock Tree Synthesis (CTS), Design for Testability (DFT), RC Extraction, and STA closure across multiple process corners.
- Multipower domain, signal integrity, and power/IR drop analysis.
- LINTing and Clock Domain Crossing (CDC) requirements.
- Functional and timing ECO methodologies, both manual and tool-driven.
- Physical Design Verification methodologies to debug LVS/DRC issues at chip/block level.
- Proficiency with industry-standard physical design tools, preferably Cadence or Synopsys.
We offer a competitive salary of approximately €120,000 per annum, commensurate with experience, plus benefits including health insurance, retirement plan, and opportunities for professional growth and development.
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