Digital Verification Expert for ICs
hace 11 horas
A Digital Verification Engineer will work on the development of the Digital Verification framework and infrastructure of complex digital and mixed-signal ICs using leading-edge technologies with industry-standard ASIC tools.
About the Role- UVM and System Verilog based Digital Verification environment definition and development
- VIPs standardization, definition, development, and documentation
- Digital Verification Metrics definition for RTL and Gate-Level Verification
- Test Plan definition and development
- Digital Verification Automation and Scripting
- Regression's infrastructure definition, development, and management
We are looking for a skilled engineer with a PhD/BS/MS in Electrical Engineering with emphasis in Digital Design/VLSI coursework. 3+ years of strong experience in both RTL and Gate-Level Verification is required.
You should be proficient in Digital Verification Industry Languages (UVM, System Verilog) and Standards, as well as have a good understanding of DV skills and areas such as Constraint random tests, SV assertions, coverage metrics, analog and digital DV modeling, DV test plans, regression analysis and reports, UVM DV Agents (Monitor, Driver, Scoreboard), etc.
What We OfferMonolithic Power Systems, Inc. (MPS) offers an estimated salary range of $120,000-$180,000 per year, depending on experience. We strive to build and maintain a culture of diversity, equity, and inclusion, and recognize that diverse voices and ideas make our company and our products stronger.
Benefits- Excellent scripting and automation skills using Python and C/C++ (TCL is a plus)
- Good written/verbal communication skills and strong teamwork/collaboration
- Knowledge/Experience with the following is a plus: Embedded designs and/or firmware development, Knowledge of power management industry/applications, I2C, I3C, SPI, PMBUS, Hi-Speed protocols (Serdes, PCIe, USB 3.0), GitLab
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