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The position requires the ability to integrate RTL code releases into new FPGA designs, configure FPGA peripherals for maximising RISC-V prototyping performance, and implement new RTL modules for optimal I/O configurations. Collaboration with cross-functional teams to understand and implement feature requirements is also essential. The ideal candidate will have experience with Xilinx (or Altera) FPGAs using Xilinx Vivado (or Altera Quartus), FPGA Integrated Logic Analyser probes, Verilog / SystemVerilog (or VHDL), and strong knowledge of AXI4 / AXI4-Lite, UART, I2C, and SPI protocols. Familiarity with FPGA timing, placement constraints, and scripting (TCL, Bash) is also required.
This is a great opportunity for a Senior FPGA engineer to contribute to a team that is driving the future of hardware development.