Junior Digital Design Engineer

hace 3 semanas

Barcelona, Barcelona, España Epsilonr A tiempo completo

Job Summary

Epsilonr is seeking a highly skilled Junior Digital Design Engineer to join our team of Design Engineers in Europe. This role requires on-site presence with no remote option available.

Key Responsibilities

  • Responsible for physical design, development, and verification of digital/mixed-signal ICs.
  • Execute chip and block floorplan/implementation, power and clock distribution, chip assembly, Place & Route (P&R), Static Timing Analysis (STA), and Layout vs. Schematic (LVS)/Design Rule Check (DRC) to closure.
  • Collaborate closely with the digital/analog design team for physical implementation and integration of custom analog blocks/interfaces/IPs.

Requirements

  • Advanced degree in Electrical Engineering, Computer Science, or equivalent.
  • Preferred 1+ years of experience in Physical Digital Design.
  • Preferred 2+ years of experience in ASIC design, verification, or related work.
  • Strong written and verbal communication skills in English, with demonstrated ability to collaborate effectively in a team environment.
  • Ability to work independently, follow design specifications, and execute tasks to meet project milestones with high quality.
  • Solid knowledge of the ASIC development process and digital design techniques.
  • Experience with programming, scripting, and automation languages like Perl, TCL, Unix, or Python.
  • Technical proficiency in: Verilog/System Verilog coding, Synthesis, Clock Tree Synthesis (CTS), Design for Testability (DFT), Extraction, and STA closure across multiple process corners.
  • Multipower domain, signal integrity, and power/IR drop analysis.
  • Linting and Clock Domain Crossing (CDC) requirements.
  • Functional and timing ECO methodologies, both manual and tool-driven.
  • Physical Design Verification methodologies to debug LVS/DRC issues at chip/block level.
  • Familiarity with industry-standard physical design tools, preferably Cadence Encounter/Innovus or Synopsys ICC/ICC2.

Desirable Skills

  • Physical SOC design involving microcontroller (uC) design (ARM/RISCV), knowledge of power management applications, familiarity with I/F protocols (I2C, SPI, USB, PMBUS, etc.).

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