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Senior ASIC Design Verification Engineer
hace 2 meses
Company: Photonic Sensors & Algorithms
Job Title: Senior ASIC Design Verification Engineer
Job Summary:
We are seeking an experienced Senior ASIC Design Verification Engineer to join our team at Photonic Sensors & Algorithms. As a key member of our Algorithms team, you will be responsible for integrating and formally verifying complex digital designs composed of multiple HDL-blocks developed by our Digital Design and Verification Groups, as well as IP-blocks from third parties.
Responsibilities:
- Integration and Formal Verification of a complex digital design composed by multiple HDL-blocks developed by members of our Digital Design and Verification Groups as well as IP-blocks from third parties.
- Porting our current algorithms to an ASIC.
- Definition of the hardware-software architecture that guarantees the lowest power consumption, as well as maximum speed and precision in the calculations.
- Development of the hardware system using Xilinx development tools for FPGAs.
- RTL coding, simulation and verification.
- Choice of the target digital process.
- RTL porting to the targeted ASIC-process.
- Development of the control software for our camera.
- C/C++ developments for embedded microprocessors (within FPGAs and ASICs).
- Development of techniques to reduce computational costs.
Requirements:
- Bachelor, Master or PhD in Telecommunication, Electronics, Computer Science or related fields.
- 5+ years' experience working on the design of complex FPGA and ASIC systems.
- Experience in RISC-V and/or ARM embedded architectures.
- Extensive experience in HDLs-Hardware Description Languages (Verilog and/or VHDL).
- Ability to integrate third party IPs.
- Development of testbenches for the verification of digital designs (Verilog, SystemVerilog, UVM...).
- Version control software such as Git or SVN.
- Signal processing in software such as Matlab, Python and/or C++.
- Analysis of complex algorithms and problems to find creative and innovative solutions.
