Staff Physical Digital Design Engineer

hace 2 semanas

Barcelona, Barcelona, España Monolithic Power Systems A tiempo completo

Job Summary: We are seeking a highly skilled Staff Physical Digital Design Engineer to join our team of Design Engineers in Europe. This role will be on-site, with no remote option available. The successful candidate will be responsible for all aspects of physical design and implementation, including establishing physical design methodologies and flow automation. As a key member of our design development team, you will work on the digital design implementation and verification of mixed-signal ICs using standard EDA tools. Our products include power management and mixed-signal functions, such as switching regulators, sensors, motor control, display drivers, audio amplifiers, and power management ICs for fast-growing portable and non-portable markets.

Key Responsibilities:

  • Responsible for physical design, development, and verification of digital/mixed-signal ICs.
  • Chip and block floorplan/implementation, power/clock distribution, chip assembly, P&R, STA, and LVS/DRC to closure.
  • Work closely with digital/analog design team for physical implementation and custom analog blocks/interface/IPs.
  • Help build an automated environment for RTL-to-PNR using high-level languages and devops-like services.

Requirements:

  • Advanced degree in Electrical Engineering/Computer Science or equivalent.
  • 7+ years (preferred) of Physical Digital Design experience.
  • 2+ years (preferred) ASIC design, verification, or related work experience.
  • Good written/verbal communication English skills and strong teamwork collaboration.
  • Ability to work independently, follow instructions according to design specifications, and execute tasks to hit milestones with quality.
  • Strong knowledge of ASIC development process and digital design techniques.
  • Experience with programming, scripting, and automation languages like Perl/TCL/Unix.
  • Strong technical abilities & understanding in these areas: Verilog/System Verilog coding, Synthesis, LEC, CTS, DFT, RC Extraction, and STA closure across multiple process corners, Multipower domain, signal integrity, & power/IR drop analysis, Linting and CDC requirements, Expertise in both hand-written and tool-driven functional/timing ECO, Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.
  • Industry physical tools: Cadence (preferred) or Synopsys.
  • SOC design including uC design (ARM/RISCV).
  • Digital on top designs using both bottom-up and top-down flows.
  • Hierarchical STA for chip top designs.
  • Advanced nodes below 16nm, FinFET.

Preferred Qualifications:

  • Statistical STA, AOCV, SI and noise analysis.
  • Knowledge of power management industry/applications.
  • I/F: I2C, SPI, USB, PMBUS, etc.
  • Advanced DFT techniques: LBIST, Delay Fault, SCAN Compression.
  • Object-oriented programming (Python, Java, etc).

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