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Staff Physical Digital Design Engineer

hace 2 meses


Barcelona, Barcelona, España Monolithic Power Systems A tiempo completo
Job Summary

We are seeking a highly skilled Staff Physical Digital Design Engineer to join our team of Design Engineers in one of our offices in Europe.

This role will be on-site, with no remote option available.

Key Responsibilities
  1. Responsible for physical design, development, and verification of digital/mixed-signal ICs.
  2. Chip and block floorplan/implementation, power/clock distribution, chip assembly, P&R, STA, and LVS/DRC to closure.
  3. Work closely with the digital/analog design team for physical implementation and custom analog blocks/interfaces/IPs.
  4. Help build an automated environment for RTL-to-PNR using high-level languages and devops-like services.
Requirements
  1. Requires an advanced degree in Electrical Engineering/Computer Science or equivalent.
  2. 7+ years (preferred) of Physical Digital Design experience.
  3. 2+ years (preferred) ASIC design, verification, or related work experience.
  4. Good written/verbal communication skills in English and strong teamwork collaboration.
  5. Ability to work independently, follow instructions according to design specifications, and execute tasks to hit milestones with quality.
  6. Strong knowledge of ASIC development process and digital design techniques.
  7. Experience with programming, scripting, and automation languages like Perl/TCL/Unix.
  8. Strong technical abilities & understanding in these areas: Verilog/System Verilog coding, synthesis, LEC, CTS, DFT, RC extraction, and STA closure across multiple process corners.
  9. Multipower domain, signal integrity, and power/IR drop analysis. Linting and CDC requirements. Expertise in both hand-written and tool-driven functional/timing ECO.
  10. Physical Design Verification methodology to debug LVS/DRC issues at chip/block level. Industry physical tools: Cadence (preferred) or Synopsys.
  11. SOC design including uC design (ARM/RISCV), Digital on top designs using both bottom-up and top-down flows, Hierarchical STA for chip top designs, Advanced nodes below 16nm, FinFET.
  12. Experience with the following is desired: Statistical STA, AOCV, SI and noise analysis, Knowledge of power management industry/applications, I/F: I2C, SPI, USB, PMBUS, etc., Advanced DFT techniques: LBIST, Delay Fault, SCAN Compression, Object-oriented programming (Python, Java, etc.), VCS: git, svn, DevOps, Continuous integration, continuous delivery, FPGA development: Xilinx (preferred), Intel, Lattice, etc.