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Senior Physical Digital Design Engineer

hace 2 meses

Barcelona, Barcelona, España Monolithic Power Systems A tiempo completo

Job Summary:

We are seeking a highly skilled Senior Physical Digital Design Engineer to join our team at Monolithic Power Systems. This role will be based in one of our European offices, with a focus on on-site work.

The successful candidate will be responsible for all aspects of physical design and implementation, including the development and verification of digital and mixed-signal ICs. In this role, you will participate in the establishment of physical design methodologies and flow automation, working closely with our design development team.

As a Physical Design Engineer, you will be responsible for the digital design implementation and verification of mixed-signal ICs using standard EDA tools. Our products include power management and mixed-signal functions, such as switching regulators, sensors, motor control, display drivers, and audio amplifiers.

Key Responsibilities:

  • Responsible for physical design, development, and verification of digital and mixed-signal ICs
  • Chip and block floorplan/implementation, power/clock distribution, chip assembly, P&R, STA, and LVS/DRC to closure
  • Work closely with digital/analog design teams for physical implementation and custom analog blocks/interface/IPs
  • Help build an automated environment for RTL-to-PNR using high-level languages and DevOps-like services

Requirements:

  • Advanced degree in Electrical Engineering/Computer Science or equivalent
  • 3-5 years of Physical Digital Design experience
  • 2+ years of ASIC design, verification, or related work experience
  • Good written/verbal communication English skills and strong teamwork collaboration
  • Ability to work independently, follow instructions according to design specifications, and execute tasks to hit milestones with quality
  • Strong knowledge of ASIC development process and digital design techniques
  • Experience with programming, scripting, and automation languages like Perl/TCL/Unix
  • Strong technical abilities and understanding in the following areas:
    • Verilog/System Verilog coding
    • Synthesis, LEC, CTS, DFT, RC Extraction, and STA closure across multiple process corners
    • Multipower domain, signal integrity, and power/IR drop analysis
    • Linting and CDC requirements
    • Expertise in both hand-written and tool-driven functional/timing ECO
    • Physical Design Verification methodology to debug LVS/DRC issues at chip/block level
    • Industry physical tools: Cadence (preferred) or Synopsys
  • Experience with the following is desired:
    • Advanced nodes below 16nm, FinFET
    • SOC design including uC design (ARM/RISCV)
    • Digital on top designs using both bottom-up and top-down flows
    • Hierarchical STA for chip top designs
    • Statistical STA, AOCV, SI, and noise analysis
    • Knowledge of power management industry/applications
    • I/F: I2C, SPI, USB, PMBUS, etc.
    • Advanced DFT techniques: LBIST, Delay Fault, SCAN Compression
    • Object-oriented programming (Python, Java, etc)
    • VCS: git, svn
    • DevOps, Continuous integration, continuous delivery
    • FPGA development: Xilinx (preferred), Intel, Lattice, etc.

Location:

  • Spain: Barcelona
  • Netherlands: Enschede/Nijmegen
  • Portugal: Porto/Lisbon