Senior Analog and Digital Verification Engineer
hace 2 semanas
**Senior Mixed Signal Verification Engineer**
We are seeking a highly skilled Senior Mixed Signal Verification Engineer to join our team at Robert Bosch Group. As a key member of our verification team, you will be responsible for developing and implementing verification strategies for our state-of-the-art SoCs.
Responsibilities:- Develop Accurate Behavioral Models: Create accurate behavioral models for mixed-signal circuits to ensure seamless integration with digital and analog components.
- Verify Performance and Accuracy: Verify the performance and accuracy of developed models against circuit-level simulations and measurements to ensure high-quality design.
- Collaborate with Cross-Functional Teams: Work closely with system architects, analog/digital designers, and other stakeholders to understand circuit specifications, design intent, and performance requirements.
- Implement Verification Plans: Develop and implement verification plans to ensure comprehensive coverage of mixed-signal circuits.
- Develop and Run System Simulations: Develop and run system simulations to verify design, analyze performance, power, and timing, and uncover bugs.
- Debug and Resolve Issues: Replicate root causes, debug issues in the pre-silicon environment, and implement corrective measures to resolve failing tests.
- Maintain and Improve Verification Infrastructure: Maintain and improve existing functional verification infrastructure and methodology to ensure efficient and effective verification processes.
- Develop Tools and Scripts: Develop tools for automated generation of verification reports and regression management to streamline the verification process.
- Master's or Bachelor's Degree in Electrical/Electronics/Computer Engineering: Possess a degree in Electrical/Electronics/Computer Engineering with at least 5 years of relevant experience in the industry.
- Strong Problem-Solving and Teamwork Skills: Demonstrate strong problem-solving and teamwork skills, as well as strong verbal and written communication skills.
- Good Working Knowledge of Verilog/SystemVerilog: Possess good working knowledge of Verilog/SystemVerilog and UVM.
- Experience with Gate Level Simulations: Have experience setting up, running, and debugging Gate Level simulations.
- Additional Skills: Proficiency in scripting languages and utilities, including Make and Python, is a plus.
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