SENIOR DIGITAL IC DESIGNER
Hace 1 semana
Madrid, Area Metropolitana (comarca); Comunidad de Madrid, España
TMRW
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Join a thriving environment tasked with delivering new and disruptive technologies
We are seeking a highly motivated and skilled Digital IC Designer to join our engineering team.
The ideal candidate will be responsible for the design, development, simulation, and verification of complex digital integrated circuits (ICs) for various applications.
on experience with the Cadence suite of Electronic Design Automation (EDA) tools to ensure designs meet performance, power, and area specifications.
RTL Design & Development: Develop and implement RTL (Register Transfer Level) code using VHDL/Verilog based on design specifications.
Launch/Incisive, SimVision) to validate performance and functionality.
Synthesis and Implementation: Work on synthesis and physical design tasks, including floorplanning, placement, clock tree synthesis, and routing using Cadence physical design platforms (e.
Timing Analysis and Signoff: Conduct static timing analysis (STA) and timing closure using tools like Cadence Tempus to ensure designs meet all timing requirements. Perform design rule checks (DRC) and layout versus schematic (LVS) verification using tools such as Cadence Pegasus or Cadence Innovus to prepare designs for fabrication (tape?Create and maintain comprehensive design documentation, technical reports, and test plans. Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with a focus on VLSI or microelectronics. Proven experience in digital IC design, with a strong portfolio of completed projects. Expertise in the Cadence digital design flow is a must, including tools like Virtuoso (for schematics/layout viewing), Genus (synthesis), Innovus (physical design), Tempus (timing analysis), and verification tools. Proficiency in hardware description languages (Verilog, VHDL). power design techniques and methodologies. Scripting skills (Tcl, Perl, Python) to automate design flows are desirable. power design methodologies and advanced optimization techniques. Strong scripting abilities (Tcl, Perl, Python) to automate design flows and improve efficiency. signal or analog/digital integration projects. Knowledge of semiconductor fabrication processes and design for manufacturability (DFM). functional engineering teams. Senior level Job FunctionEngineering and Design #
Timing Analysis and Signoff: Conduct static timing analysis (STA) and timing closure using tools like Cadence Tempus to ensure designs meet all timing requirements. Perform design rule checks (DRC) and layout versus schematic (LVS) verification using tools such as Cadence Pegasus or Cadence Innovus to prepare designs for fabrication (tape?Create and maintain comprehensive design documentation, technical reports, and test plans. Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with a focus on VLSI or microelectronics. Proven experience in digital IC design, with a strong portfolio of completed projects. Expertise in the Cadence digital design flow is a must, including tools like Virtuoso (for schematics/layout viewing), Genus (synthesis), Innovus (physical design), Tempus (timing analysis), and verification tools. Proficiency in hardware description languages (Verilog, VHDL). power design techniques and methodologies. Scripting skills (Tcl, Perl, Python) to automate design flows are desirable. power design methodologies and advanced optimization techniques. Strong scripting abilities (Tcl, Perl, Python) to automate design flows and improve efficiency. signal or analog/digital integration projects. Knowledge of semiconductor fabrication processes and design for manufacturability (DFM). functional engineering teams. Senior level Job FunctionEngineering and Design #