Principal Engineer, Design Verification

hace 1 día

Valencia, España Information Technology Association Galway A tiempo completo
Principal Engineer, Design Verification

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Locations: United Kingdom, Edinburgh, SC, Freer; Spain, Valencia, Cortes Valencianas; United Kingdom, Newbury; Ireland, Cork; Ireland, Limerick

Time Type: Full time

Posted On: Posted 10 Days Ago

Job Requisition ID: R243314

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $12 billion in FY23 and approximately 26,000 people globally working alongside 125,000 global customers, ADI ensures today’s innovators stay Ahead of What’s Possible. Learn more at www.analog.com and on LinkedIn and Twitter (X).

The Group:

The Custom Silicon Power (CSP) team is primarily focused on PMIC and hybrid Mixed-Signal / Power developments, for High-End / High-Volume electronic devices, such as Smartphones, Tablets, and Consumer Accessories.

The Position:

  • Verification of key digital blocks in differentiated mixed signal SOCs targeted for the consumer market.
  • Complete verification ownership – Testbench Architecture, Testplan and Testbench Development, Functional Coverage Closure, and Code Coverage Closure.
  • Usage of industry standard methodologies like UVM and constrained random approach to achieve verification goals.
  • Actively explore and deploy techniques like Formal verification to achieve faster turnaround time on verification.
  • Debug efficiently and clearly articulate gating issues to engineering leads.
  • Integrate the block level testbench at SOC level and verify SOC integration.
  • Involvement in post-silicon activities such as silicon bring-up, evaluation support, ATE pattern bring-up to take SoC into production.

Desired Qualifications & Experience:

  • Electronic Engineering/Computer Engineering degree with 10+ years of progressive experience in Verification.
  • Demonstrated experience in developing UVM-based testbench infrastructure, functional cover point development, code coverage analysis/closure, and assertion development.
  • Strong understanding and experience of Verilog and System Verilog.
  • Excellent debug and problem-solving skills.
  • Experience with both IP and SOC level verification.
  • Self-motivated, diligent, and has an eye for detail.
  • Knowledge in AHB/AXI/APB/SPMI protocols is desirable; experience in Power aware simulations or Formal Verification is a big plus.
  • Experience in Verilog-AMS, analog behavior modelling is desirable.
  • Understanding of Buck-Boost/Inverse Buck-Boost, LDOs, BG reference concepts in the form of projects or coursework is a plus.
  • Proficiency in scripting languages and utilities including Makefile, Python, Perl, etc.
  • Good written and verbal communication skills.

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Job Req Type: Experienced

Required Travel: Yes, 10% of the time

Shift Type: 1st Shift/Days

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