Senior Design Verification Engineer

hace 1 semana

Valencia, España Analog Devices, Inc. A tiempo completo

Senior Design Verification Engineer Locations: Poland, Krakow; Spain, Valencia, Cortes Valencianas; Ireland, Cork

Time Type: Full time

Posted on: Posted 2 Days Ago

Job Requisition ID: R243973

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $12 billion in FY23 and approximately 26,000 people globally working alongside 125,000 global customers, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and Twitter (X).

Job Description: The charter of ADI's CSS team is to lead the market in selected technology domains with highly differentiated sensing and signal processing solutions. We are seeking to fill key roles in defining, developing, and verifying digital systems for this key market area. This role encompasses the entire development cycle from concept phase through design, verification, implementation, and release of products to customers. The Design Verification Engineer will collaborate with the wider ADI technical community, providing opportunities to work with many business units in ADI and exposure to various technologies and products.

Responsibilities: Verification of complex designs and sub-systems using leading edge verification methodologies. Contribute and influence decisions on methodologies/strategies to be adopted for verification. Strong knowledge of test-plan generation, coverage analysis, transaction level modeling, pseudo and constrained random techniques, assertion-based and formal verification techniques with System Verilog. Proficient in developing unit and SoC level test benches using UVM. Integrate the block testbench in chip-level UVM environment and verify integration. Define test-plans, tests, and verification methodology for block/chip-level verification. Work with the design team in generating test-plans and closure of code and functional coverage. Debugging of Gate Level Simulation (GLS), waiving Timing Violations approved by the designer. Continuous interaction with analog co-simulation and firmware team. Managing scripts written in TCL/Perl/Python for different verification aspects. Coding in C tests on M3 Series Cortex-based products. Support post-silicon verification activities of the products working with design, product evaluation, and applications engineering teams. Qualifications: Bachelor's or master's degree in Engineering (Electronic Engineering) or equivalent. Excellent debugging and analytical skills. 5-10 years in ASIC design verification. Experience with HW emulation or FPGA prototyping. Self-motivated and enthusiastic with a strong level of English speaking and writing. #LI-CC1

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

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