Senior Physical Design Engineer

**Meet the Team**

Join the Silicon One Team at Cisco, a group at the forefront of developing Cisco's groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As part of our team, you will contribute to defining cutting-edge Physical Design methodologies and creating robust flows essential for developing our complex chips. You will also have the opportunity to work hands-on with the Physical Design of intricate chip partitions.

**Your Impact**

This role offers a unique opportunity to make a significant impact at the intersection of hardware and software development, specifically supporting the Cisco Silicon One initiative. If you are passionate about exploring diverse technical domains and contributing to the core mission of hardware innovation, this position is for you. You will play a pivotal role in building tools and systems that accelerate and optimize the creation of Cisco's next-generation silicon solutions. Beyond the technical challenge, you'll be part of a team that changes the world, passionate about the brand you represent. You'll collaborate with leaders, partner with mentors, and develop incredible relationships with colleagues in a supportive environment where teamwork and collective success are prioritized.

**Responsibilities**:

- Engage in full chip physical implementation, covering the process from RTL to GDSII, and collaborate with Front-End teams to understand design architecture for effective implementation.
- Perform gate-level netlist synthesis (physical synthesis) and execute physical implementation tasks such as floorplanning, placement, Clock Tree Synthesis (CTS), and routing.
- Optimize design for power, performance, and area, and conduct formal verification to ensure design integrity.
- Perform Static Timing Analysis (STA), complete physical verification, and achieve signoff closure.
- Analyze and resolve Electromigration (EM) and IR-drop (IR) issues to meet signoff requirements.

**Minimum Qualifications**:

- B.Sc./M.Sc in Electrical Engineering, Computer Science, or any other relevant field.
- Proven experience in ASIC physical design and verification,
- Knowledge and experience in block-level synthesis, place, and route, timing closure.
- Knowledge of industry-standard PnR and signoff tools and their capabilities.

**Preferred Qualifications**:

- Deep understanding of all aspects of Physical construction and Integration.
- Knowledge in Physical Design Verification methodology LVS/DRC.
- Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
- Understanding of Static Timing Analysis, timing closure, and design constraints.
- Experience in scripting languages like Tcl, Python, Perl.

**#WeAreCisco**

WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all.

Our passion is connection—we celebrate our employees’ diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best.

We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer—80 hours each year—allows us to give back to causes we are passionate about, and nearly 86% do

U.S. employees have **access** to quality medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, short and long-term disability coverage, basic life insurance and numerous wellbeing offerings.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components. For quota-based incentive pay, Cisco typically pays as follows:
.75% of incentive target for each 1% of revenue attainment up to 50% of quota;
1.5% of incentive target for each 1% of attainment between 50% and 75%;
1% of incentive target for each 1% of attainment between 75% and 100%; and once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.