Research Engineer

Job Reference

780_24_CS_V_RE1



Position

Research Engineer - Verification for RISC-V cores and accelerators (RE1)



Closing Date

Saturday, 16 November, 2024




About BSC

The Barcelona Supercomputing Center - Centro Nacional de Supercomputación (BSC-CNS) is the leading supercomputing center in Spain. It houses MareNostrum, one of the most powerful supercomputers in Europe, and is now hosting entity for EuroHPC JU, the Joint Undertaking that leads large-scale investments and HPC provision in Europe. The mission of BSC is to research, develop and manage information technologies in order to facilitate scientific progress. BSC combines HPC service provision and R&D into both computer and computational science (life, earth and engineering sciences) under one roof, and currently has over 1000 staff from 60 countries. We are particularly interested for this role in the strengths and lived experiences of women and underrepresented groups to help us avoid perpetuating biases and oversights in science and IT research. In instances of equal merit, the incorporation of the under-represented sex will be favoured. We promote Equity, Diversity and Inclusion, fostering an environment where each and every one of us is appreciated for who we are, regardless of our differences. If you consider that you do not meet all the requirements, we encourage you to continue applying for the job offer. We value diversity of experiences and skills, and you could bring unique perspectives to our team.


Context And Mission

BSC is constructing a full RISCV ecosystem, from the design of the processors to the tape-out of them; also, BSC is working in the full software stack. In this context, BSC has to develop an out-of-order RISCV processor supporting the vector extension. This vacancy is for a junior verification engineer to work on the verification for this processor and accelerator.


Key Duties

You will use your design and verification expertise to verify complex digital designs, focused on vector units and other accelerators.
You will collaborate closely with design and verification engineers in active projects and perform hands-on verification, and contribute to design, build, and integrate the designs.
Using your UVM, SystemVerilog and problem-solving skills, you will build efficient and effective verification environments that exercise processor designs through their corner-cases and expose all types of bugs.
You will be involved in the full life cycle of verification, including verification planning, test and assertion implementation, failure triaging, debugging, coverage definition and others.



Requirements

Education

BS or MS degree in Electrical Engineering, Computer Engineering, or equivalent.

Essential Knowledge and Professional Experience

Experience using Universal Verification Methodology(UVM), simulating, debugging, and documenting results
Knowledge of and experience with industry-standard simulators (Model/QuestaSim, VCS, etc.), revision control systems and regression systems.
Experienced in several key DV methodologies: UVM, SystemVerilog Assertions, functional coverage, Assembly/C-based random/constrained-random Verification, Formal Verification, Verification IPs.
Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage measures to identify verification holes and to show progress towards tape-out.
Strong debugging skills and able to work with design engineers to deliver functionally correct design blocks. Execute tests. Analyze data, prepare reports summarizing results and statistics.
Scripting experience using scripting languages like Python, Perl, Bash or Tcl to perform support adjustments and customization of design and verification flows. Familiarity with Linux.
Excellent interpersonal, written, and verbal communication skills.
Ability to work as part of a cross-functional team according to an established timeline
Fluency in English is essential, Spanish is welcome.

Additional Knowledge and Professional Experience

Deep understanding of Modern in-order and out-of-order processor core microarchitecture and accelerator designs.
Experience with one or more Instruction Set Architectures (ISAs) including RISC-V, and their implementation within in-order and out-of-order processor cores.
Experience with vector architectures, in particular implementing the RISC-V V-extension.

Competences

The candidate must be an effective communicator, multitask, and work well on collaborative designs.
Keeps abreast of technology trends.
Ability to think creatively.
Ability to work independently and make decisions.
Ability to take initiative, prioritize and work under set deadlines.



Conditions

The position will be located at BSC within the Computer Sciences Department
We offer a full-time contract (37.5h/week), a good working environment, a highly stimulating environment with state-of-the-art infrastructure, flexible working hours, extensive training plan, restaurant tickets, private health insurance, support to the relocation procedures
Duration: Open-ended contract due to technical and scientific activities linked to the project and budget duration
Holidays: 23 paid vacation days plus 24th and 31st of December per our collective agreement
Salary: we offer a competitive salary commensurate with the qualifications and experience of the candidate and according to the cost of living in Barcelona
Starting date: 27/11/2023



Applications procedure and process

All applications must be made through BSC website and contain:

A full CV in English including contact details
A Cover Letter with a statement of interest in English, including two contacts for further references - Applications without this document will not be considered


In accordance with the OTM-R principles, a gender-balanced recruitment panel is formed for every vacancy at the beginning of the process. After reviewing the content of the applications, the panel will start the interviews, with at least one technical and one administrative interview. A profile questionnaire as well as a technical exercise may be required during the process. The panel will make a final decision and all candidates who had contacts with them will receive a feedback with details on the acceptance or rejection of their profile.



Deadline

The vacancy will remain open until a suitable candidate has been hired. Applications will be regularly reviewed and potential candidates will be contacted.



OTM-R principles for selection processes

BSC-CNS is committed to the principles of the Code of Conduct for the Recruitment of Researchers of the European Commission and the Open, Transparent and Merit-based Recruitment principles (OTM-R). This is applied for any potential candidate in all our processes, for example by creating gender-balanced recruitment panels and recognizing career breaks etc. BSC-CNS is an equal opportunity employer committed to diversity and inclusion. We are pleased to consider all qualified applicants for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or any other basis protected by applicable state or local law.





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