Design Verification Engineer Intern

hace 1 semana

València, España Analog Devices A tiempo completo

Are you a problem solver looking for a hands-on internship position with a market-leading company that will help develop your career and reward you intellectually and professionally? About Analog Devices Analog Devices, Inc. (NASDAQ: ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at and on and. At ADI, you will learn from the brightest minds who are here to help you grow and succeed. During your internship, you will make an impact through work on meaningful projects alongside a team of experts. Collaborating with colleagues in an environment of respect and responsibility, you will create connections that will become a part of your professional network. ADI’s culture values aligned goals, work-life balance, continuous and life-long learning opportunities, and shared rewards. The internship program features various lunch-and-learn topics and social events with other interns and full-time employees. At ADI, our goal is to develop our interns so they are the first to be considered for full-time roles. Apply now for the opportunity to grow your career and help innovate ahead of what’s possible. Responsibilities: Verification Planning: Develop and execute comprehensive verification plans, including testbench architecture, test cases, and coverage metrics. Testbench Development: Create efficient and reusable testbench environments using industry-standard methodologies (e.g., UVM, OVM). Test Case Generation: Generate directed and constrained random test cases to thoroughly exercise the design's functionality. Coverage Analysis: Analyze coverage metrics and identify areas for improvement to ensure complete verification. Debugging and Troubleshooting: Diagnose and resolve design issues, working closely with design engineers to identify root causes and propose solutions. Mentorship: Provide guidance and mentorship to junior engineers, fostering a collaborative and learning environment. Technical Leadership: Contribute to technical discussions, reviews, and decision-making processes. Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, or a related field. Proficiency in SystemVerilog, UVM, and other relevant verification languages and tools. Experience with coverage driven verification. Hands on experience in developing, updating and debugging of Verilog, SV-UVM , SOC level testbenches is a must. Strong problem-solving, analytical, and debugging skills. Excellent communication and collaboration skills. Preferred Qualifications: Master's degree or higher in a related field. Formal verification experience (Jasper Gold preferred) Experience with RISC-V systems. C/C++. Knowledge of scripting languages (e.g., Python, Perl). Familiarity with industry standards and best practices. Job Req Type: Internship/CooperativeRequired Travel: Yes, 10% of the time

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