Senior Design Verification Engineer

Senior Design Verification EngineerSenior Design Verification Engineer – Analog DevicesAbout Analog DevicesAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. The company combines analog, digital, and software technologies into solutions that help advance digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue exceeding $9 billion in FY24 and approximately 24,000 employees worldwide, ADI ensures today’s innovators stay ahead of what’s possible.Job OverviewThe ADI ADC team is seeking a motivated and experienced design verification engineer to support our ADG BU located in Valencian Community, Spain. As a Senior Design Verification Engineer, you will drive the verification strategy, plan, and execution for complex analogue and mixed‑signal blocks and systems.ResponsibilitiesPlan, develop, document, and execute verification plans across multiple platforms, including simulation and emulation.Build and enhance SystemVerilog UVM‑based simulation environments, infrastructure, and verification flows at block, subsystem, and full‑chip levels.Develop, simulate, and debug constrained‑random and directed test cases aligned with verification plans.Define and implement functional coverage models, assertions, and metrics to measure verification progress and closure.Drive verification reviews, analyze coverage results, and implement actions to close gaps and ensure completeness.Evaluate and unify different verification methodologies while continuously improving productivity and efficiency.Collaborate with global verification teams to integrate internal and third‑party IP/VIP into the verification environment.Partner with cross‑functional teams (design, architecture, software, implementation) to ensure robust design quality and timely project execution.QualificationsMaster’s degree in Computer/Electrical engineering or related field with a strong background in digital design and verification.Experience with object‑oriented programming, SystemVerilog/UVM, Python, and Perl.Experience with Cadence, Synopsys, and/or Mentor tools for simulation.Experience with System and Digital modeling languages (MATLAB or SystemC).Overall exposure to the design/verification tape‑out cycle is desirable.Prior experience working with multi‑site teams and third‑party VIP will be valuable.Export LicensingFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce – Bureau of Industry and Security and/or the U.S. Department of State – Directorate of Defense Trade Controls. Applicants for this position – except U.S. Citizens, Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.Equal OpportunityAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender identity or expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, or political affiliation, or any other legally protected group.Job DetailsLocation: Paterna, Valencian Community, SpainShift Type: 1st Shift/DaysRequired Travel: Yes, 10% of the timeEmployment Type: Full‑timeSeniority Level: Mid‑Senior levelJob Req Type: ExperiencedReferrals increase your chances of interviewing at Analog Devices.#J-18808-Ljbffr