Engineer, Design Verification

About Corinex:At Corinex, we are driving the future of energy with cutting-edge Broadband over Power Line (BPL) technology. As a global leader in smart grid solutions, we enable utilities to enhance grid visibility, flexibility, and decarbonization- supporting the seamless integration of renewable energy, electric vehicles, and heat pumps into the power grid. Headquartered in Vancouver, Canada, Corinex is the market leader in Europe, particularly in Spain, where our BPL solutions are deployed by major DSOs (Distribution System Operators) to improve grid operations. With successful implementations across global markets, our technologies accelerate the transition to a more sustainable, decentralized, and efficient energy infrastructure. Recognized as a key contributor to industry standards and a 2024 Deloitte Technology Fast 50 winner, Corinex is shaping the future of smart energy. To strengthen our team in Spain, we are seeking an experienced and motivated Engineer, Design Verification. About the role:We are seeking an Engineer, Design Verification to join our Valencia R&D team. For this role, we are open to new grads or candidates with experience. The candidate will be integrated into a dynamic, cross-functional, experienced team to do functional verification tests in Verilog and C, for million-plus gate ASICs targeted for BPL networking applications. Work directly with ASIC and board designers to ensure a smooth transition from project definition through prototyping to mass production. Define and implement test procedures to ensure the maximum level of product quality. Improve manufacturing yields and costs through creative thinking and innovative ideas.This full-time, remote position will involve working with cutting-edge semiconductor technologies, particularly high-speed networking and embedded systems.  Responsibilities: Verify highly complex SoCs and support verification development. Architect and develop the functional verification environment, including reference models, testbench development, and testcase execution. Write test plans using random techniques and coverage analysis Work closely with mixed signal teams for integration of high-speed analog behavioural models Debug failures and work with designers to resolve issues Cooperate with Synthesis, DFT, STA, and PnR to implement subsystems that meet challenging PPA requirements. Support Emulation, functional ATE, and silicon validation teams. Qualifications: Bachelor's or Master's degree in Electrical Engineering, Microelectronics, or a related field.Proficiency in verification languages, including UVM and System Verilog. Experience with block, cluster/subsystem, and top-level verification. Hands-on experience in test bench development, including agents, drivers, checkers, and interfaces for complex designs. Strong understanding of verification methodologies such as test plan creation, direct and random test cases, formal test cases, and coverage analysis. Full-cycle verification experience, from architecture to tape-out, with expertise in test plan development, debugging, coverage closure, and gate-level simulation. Proven experience in top-level verification of complex SoC designs. Expertise in high-speed protocols, particularly Ethernet. Proficiency in scripting languages such as Python and Bash. Knowledge in one or more domains: networking, embedded systems architecture, computer architecture, and machine learning accelerators. General understanding of IC design, design-for-test (DFT), and design-for-manufacturing (DFM). Familiarity with digital design methodologies, ASIC design flows, and industry-leading verification EDA tools. Ability to work effectively in a collaborative team environment. Strong communication skills in English.