Digital Verification Engineer for RISC-V Architecture

hace 7 días

Barcelona, Barcelona, España Barcelona Supercomputing Center (Bsc) A tiempo completo

**About Us**

The Barcelona Supercomputing Center - Centro Nacional de Supercomputación (BSC-CNS) is a leading supercomputing center in Spain, housing MareNostrum, one of the most powerful supercomputers in Europe. We are an entity for EuroHPC JU and lead large-scale investments and HPC provision in Europe.

We are committed to research, development, and management of information technologies to facilitate scientific progress. Our mission is to combine HPC service provision and RD into both computer and computational science under one roof, with over 1000 staff from 60 countries.

We promote Equity, Diversity, and Inclusion, fostering an environment where each and every one of us is appreciated for who we are, regardless of our differences.

Job Overview

We are seeking talented and motivated professionals with expertise in Design Verification for a chip integrating a European HPC accelerator in the context of the DARE Project and other related research projects.

The design is based on RISC-V architecture, and we need someone to verify the functional correctness of the chip for success.

Key Responsibilities

  • You will use your design and verification expertise to verify complex RISC-V digital designs, focused on a system that integrates vector units and scalar processors, and possibly other accelerators.
  • You will collaborate closely with design and verification engineers in active projects and perform hands-on verification.
  • Using your UVM, SystemVerilog, and problem-solving skills, you will build efficient and effective verification environments.
  • You will be responsible for the full life cycle of verification, including verification planning, test and assertion implementation, failure triaging, debugging, coverage definition, and others.
  • You will automatize the processes by creating and maintaining verification post-processing scripts.
  • You will train others in the configuration, deployment, use, and/or maintenance of verification software, scripts, and workflows.
  • You will supervise, guide, and coordinate the work of less experienced Verification engineers.
  • You will define and implement coverage plans for the design, and analyze the code and functional coverage results.

Requirements

  • BS degree in Electrical Engineering, Computer Engineering, or equivalent.
  • Experience with the full verification life cycle from test planning to sign-off.
  • Working knowledge of Universal Verification Methodology (UVM), writing test plans, simulating, debugging, and documenting results.
  • Knowledge of and experience with industry-standard simulators (Model/QuestaSim, VCS, etc.).
  • Experience in key DV methodologies: UVM, cosimulation, SystemVerilog Assertions, functional coverage, Verification IPs.
  • Strong debugging and triaging skills and ability to work with design engineers.
  • Strong scripting experience using languages like Python, Perl, Bash, or Tcl.
  • Experience in the implementation of SystemVerilog UVM testbenches for a complex digital design.
  • Excellent interpersonal, written, and verbal communication skills.
  • Ability to work as part of a cross-functional team according to an established timeline.

Benefits

  • A competitive salary of €85,000 per annum, commensurate with qualifications and experience.
  • A full-time contract (37.5 hours/week).
  • A good working environment.
  • Flexible working hours.
  • An extensive training plan.

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