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Power Optimization Engineer
hace 2 meses
Job Overview
We are seeking a highly skilled Power Optimization Engineer to join our team in Barcelona, Spain. As a key member of our Analog Architecture team, you will play a crucial role in designing and optimizing power architectures for SoC designs.
Key Responsibilities
- Power Architecture Design: Design and develop power architectures that optimize energy efficiency and minimize power consumption.
- Low-Power Design Techniques: Apply low-power design techniques, including multiple voltage domains, clock gating, power gating, and dynamic voltage-frequency scaling (DVFS), to minimize power consumption.
- Simulation and Verification: Use simulators and design flows to simulate and verify the performance of our SoC designs.
- Collaboration and Communication: Collaborate with cross-functional teams to ensure seamless integration of power architectures into our SoC designs.
Requirements
- 5+ years of experience in IP/SoC design.
- Excellent knowledge of energy-efficient chip/system design fundamentals and related trade-offs.
- Solid understanding of low-power design techniques, including multiple voltage domains, clock gating, power gating, and dynamic voltage-frequency scaling (DVFS).
- Proficient skills in simulators and design flows used in modern SoC designs, such as analog and AMS simulators.
Compensation Package
We offer a competitive salary of approximately €80,000 per year, based on your experience and qualifications, plus additional benefits, including health insurance, retirement plans, and paid time off.
